參數(shù)資料
型號： TLV320AIC27IPFB
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP48
封裝： PLASTIC, TQFP-48
文件頁數(shù)： 35/54頁
文件大?。?/td> 732K
代理商： TLV320AIC27IPFB
TLV320AIC27
STEREO AUDIO CODEC
SLAS253A – MARCH 2000 – REVISED SEPTEMBER 2000
40
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
six-channel I2S mode
In this mode, the device now has six-channel support and GPIO capability. Rear and LFE center DAC data is
mapped onto the GPIO output pins as I2S data when these data slots are tagged as valid. The I2S enable bit
is set in register 5Ah. Enabling of I2S overrides the GPIO function.
six-channel I2S mode features
D Vendor ID reads back as TXN3
D ADC and DAC conversion channels provided
D Rear and LFE/center DAC slots flagged as supported in extended audio capability register 28h
D GPIO capability supporting bits 11–13 flagged as supported
D Master/slave ID0/1 supported
D Surround audio data not sent to the DACs is sent from the GPIO pins in I2S format, at 48 ksps rate (no
variable rates supported by the I2S outputs).
D Headphone/line level outputs duplicating the main outputs supported, with gain control from register 04h.
D 3D stereo enhanced sound supported
D Master volume control register maps to the location dependant on selected ID: ID 00 or 01 uses master
volume at register 02h, ID 10 uses 38h (surround volume), and ID 11 uses 36h (LFE, center volume). In
this case, bits 7 and 15 act as left and right mute.
GPIO pins and I2S
The AC’97 Revision 2.1 specification has provisions for up to 16 programmable IO pins. Within the 48-pin TQFP
package used, provision has been made for three pins to be used as GPIO pins. These pins (numbers 43, 44,
48) are also used as I2S output pins to support multichannel operation.
When pins 43, 44, and 48 are used as GPIO pins, they are mapped onto bits 11, 12, and 13, respectively, in
the ac-link slot 12. These optional locations may be configured in any way—as inputs or outputs, as supporting
interrupt operation, etc., offering maximum flexibility to the user. The appropriate GPIO control registers are
supported to control these pins.
When pins 43, 44, and 48 are used as I2S pins, pin 48 becomes the shared LRCLK with frequency fixed at 48
kHz, and pins 43 and 44 become the output data clocked out at the BITCLK rate. Thus, to connect an external
DAC, configure it in I2S mode as follows:
Connect BITCLK signal from the TLV320AIC27 to SCLK on the DAC.
Connect BITCLK from the AC’97 to BCLK on the DAC.
Connect pin 48 from the TLV320AIC27 to LRCLK on the DAC.
Connect one of the two data pins, 43 or 44, on TLV320AIC27 to the SDATA pin on the DAC.
Note that the DAC must support serial interface data rates of up to 12.5 MHz. This is supported by Texas
Instruments DAC product line.
I2S is enabled when GPIO is not enabled (GPIO Bit 0 is enabled in register 3Eh) and vendor-specific I2S (bit
7) in register 5Ah is set.
Table 22 shows the connections to a typical I2S compatible stereo DAC.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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TLV320AIC28EVM 功能描述:音頻 IC 開發(fā)工具 TLV320AIC28 Eval Mod RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評估:TAS5614L 工作電源電壓:12 V to 38 V
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