參數(shù)資料
型號(hào)： TLV320AIC27IPFB
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP48
封裝： PLASTIC, TQFP-48
文件頁數(shù)： 18/54頁
文件大小： 732K
代理商： TLV320AIC27IPFB
TLV320AIC27
STEREO AUDIO CODEC
SLAS253A – MARCH 2000 – REVISED SEPTEMBER 2000
25
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
ac-link audio input frame (SDATA_IN) (continued)
slot 2: status data port
The status data port delivers 16-bit control register read data.
Bit (19:4)
Control register read data
Bit (3:0)
Reserved (stuffed with 0s)
If slot 2 is tagged invalid by the TLV320AIC27, then the entire slot is stuffed with 0s by the TLV320AIC27.
slot 3: PCM record left channel
Audio input frame slot 3 is the left channel output of the TLV320AIC27’s input mux, post-ADC.
The TLV320AIC27’s ADCs can be implemented to support 16, 18, or 20-bit resolutions. The TLV320AIC27
sends out its ADC output data (MSB first), and stuffs any trailing invalid bit positions with 0s to fill out its 20-bit
time slot.
slot 4: PCM record right channel
Audio input frame slot 4 is the right channel output of the TLV320AIC27’s input mux, post-ADC.
The TLV320AIC27’s ADCs can be implemented to support 16, 18, or 20-bit resolutions. The TLV320AIC27
sends out its ADC output data (MSB first), and stuffs any trailing invalid bit positions with 0s to fill out its 20-bit
time slot.
slot 5: optional modem line1 codec
Slot 5 is not supported.
slot 6: optional dedicated microphone record data
Audio input frame slot 6 is an optional (post-ADC) third PCM system input channel available for dedicated use
by a desktop microphone. This optional AC’97 feature is not supported by the TLV320AIC27. This can be
determined by the AC’97 controller interrogating the TLV320AIC27 vendor ID register.
slot 7 to 11: reserved
Audio input frame slots 7 to 12 are reserved for future use and are always stuffed with 0s by the TLV320AIC27.
slot 10: optional modem line2 codec
Slot 10 is not supported.
slot 12:
GPIO functions supported.
ac-link low-power mode
The ac-link signals can be placed in a low-power mode. When the TLV320AIC27’s power-down register 26h
is programmed to the appropriate value, both BIT_CLK and SDATA_IN are brought to and held at a logic-low
voltage level.
BIT_CLK and SDATA_IN transition to low occurs immediately following the decode of the write to the
power-down register 26h with PR4. When the AC’97 controller driver is ready to program the ac link into its
low-power mode, slots 1 and 2 are assumed to be the only valid stream in the audio output frame. At this point
it is assumed that all sources of audio input have also been neutralized.
The AC’97 controller should also drive SYNC and SDATA_OUT low after programming the TLV320AIC27 to
this low-power, halted mode.
Once the TLV320AIC27 has been instructed to halt BIT_CLK, a special wake up protocol must be used to bring
the ac link to the active mode, since normal audio output and input frames can not be communicated in the
absence of BIT_CLK.
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