- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98254 > TLV320AIC3111IRHBR (TEXAS INSTRUMENTS INC) AUDIO AMPLIFIER, PQCC32 PDF資料下載
參數(shù)資料
| 型號： | TLV320AIC3111IRHBR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 音頻／視頻放大 |
| 英文描述： | AUDIO AMPLIFIER, PQCC32 |
| 封裝： | 5 X 5 MM, GREEN, PLASTIC, QFN-32 |
| 文件頁數(shù)： | 108/156頁 |
| 文件大小： | 1701K |
| 代理商： | TLV320AIC3111IRHBR |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁當前第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁
www.ti.com
SLAS644B – JULY 2009 – REVISED OCTOBER 2009
5.6.4.2
DRC Hysteresis
DRC hysteresis is programmable by writing to page 0 / register 68, bits D1–D0. These bits can be
programmed to represent values between 0 dB and 3 dB in steps of 1dB. It is a programmable window
around the programmed DRC threshold that must be exceeded for the disabled DRC to become enabled,
or the enabled DRC to become disabled. For example, if the DRC threshold is set to –12 dBFS and the
DRC hysteresis is set to 3 dB, then if the gain compression in the DRC is inactive, the output of the DAC
digital volume control must exceed –9 dBFS before gain compression due to the DRC is activated.
Similarly, when the gain compression in the DRC is active, the output of the DAC digital volume control
must fall below –15 dBFS for gain compression in the DRC to be deactivated. The DRC hysteresis feature
prevents the rapid activation and de-activation of gain compression in the DRC in cases when the output
of the DAC digital volume control rapidly fluctuates in a narrow region around the programmed DRC
threshold. By programming the DRC hysteresis as 0 dB, the hysteresis action is disabled.
The recommended value of DRC hysteresis is 3 dB.
5.6.4.3
DRC Hold
DRC hold is intended to slow the start of decay for a specified period of time in response to a decrease in
energy level. To minimize audible artifacts, it is recommended to set the DRC hold time to 0 through
programming page 0 / register 69, bits D6–D3 = 0000.
5.6.4.4
DRC Attack Rate
When the output of the DAC digital volume control exceeds the programmed DRC threshold, the gain
applied in the DAC digital volume control is progressively reduced to avoid the signal from saturating the
channel. This process of reducing the applied gain is called attack. To avoid audible artifacts, the gain is
reduced slowly with a rate equaling the attack rate, programmable via page 0 / register 70, bits D7–D4.
Attack rates can be programmed from 4-dB gain change per 1/DAC_fS to 1.2207e–5-dB gain change
per 1/DAC_fS.
Attack rates should be programmed such that before the output of the DAC digital volume control can clip,
the input signal should be sufficiently attenuated. High attack rates can cause audible artifacts, and
too-slow attack rates may not be able to prevent the input signal from clipping.
The recommended DRC attack rate value is 1.9531e–4 dB per 1/DAC_fS.
5.6.4.5
DRC Decay Rate
When the DRC detects a reduction in output signal swing beyond the programmed DRC threshold, the
DRC enters a decay state, where the applied gain in the digital-volume control is gradually increased to
programmed values. To avoid audible artifacts, the gain is slowly increased with a rate equal to the decay
rate programmed through page 0 / register 70, bits D3–D0. The decay rates can be programmed from
1.5625e–3 dB per 1/DAC_fS to 4.7683e–7 dB per 1/DAC_fS. If the decay rates are programmed too high,
then sudden gain changes can cause audible artifacts. However, if it is programmed too slow, then the
output may be perceived as too low for a long time after the peak signal has passed.
The recommended value of DRC decay rate is 2.4414e–5 dB per 1/DAC_fS.
Copyright 2009, Texas Instruments Incorporated
APPLICATION INFORMATION
55
Product Folder Link(s): TLV320AIC3111
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TLV320AIC3120IRHBR | AUDIO AMPLIFIER, PQCC32 |
| TLV320AIC3120IRHBT | AUDIO AMPLIFIER, PQCC32 |
| TLV320AIC31IRHBRG4 | SPECIALTY CONSUMER CIRCUIT, PQCC32 |
| TLV320AIC31IRHBR | SPECIALTY CONSUMER CIRCUIT, PQCC32 |
| TLV320AIC31IRHBTG4 | SPECIALTY CONSUMER CIRCUIT, PQCC32 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TLV320AIC3111IRHBT | 功能描述:接口—CODEC Low-Pwr Audio CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TLV320AIC3120 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Low-Power Mono Audio Codec With Embedded miniDSP and Mono Class-D Speaker Amplifier |
| TLV320AIC3120EVM-U | 功能描述:音頻 IC 開發(fā)工具 TLV320AIC3120EVM-U Eval Mod RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評估:TAS5614L 工作電源電壓:12 V to 38 V |
| TLV320AIC3120IRHBR | 功能描述:接口—CODEC Low-Pwr Audio CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TLV320AIC3120IRHBT | 功能描述:接口—CODEC Low-Pwr Audio CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。