參數(shù)資料
型號： TLV320AIC36IZQER
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PBGA80
封裝： 5 X 5 MM, PLASTIC, VFBGA-80
文件頁數(shù)： 25/168頁
文件大小： 1452K
代理商： TLV320AIC36IZQER
SBAS387A – MAY 2009 – REVISED JUNE 2010
www.ti.com
(continued)
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D5–D2
R/W
00 00
GPIO4/DIGMIC_DATA Control
0000: GPIO4/DIGMIC_DATA input/output disabled
0001: GPIO4/DIGMIC_DATA input is used for secondary BCLK, secondary WCLK, secondary DIN
or secondary ADC_WCLK input
0010: GPIO4/DIGMIC_DATA is general purpose input (GPI)
0011: GPIO4/DIGMIC_DATA is general purpose output
0100: GPIO4/DIGMIC_DATA output is CLKOUT
0101: GPIO4/DIGMIC_DATA output is INT1 (active high)
0110: GPIO4/DIGMIC_DATA output is inverted INT1 (active low)
0111: GPIO4/DIGMIC_DATA output is INT1 (open drain)
1000: GPIO4/DIGMIC_DATA output is INT2 (active high)
1001: GPIO4/DIGMIC_DATA output is inverted INT2 (active low)
1010: GPIO4/DIGMIC_DATA output is INT2 (open drain)
1011: GPIO4/DIGMIC_DATA output is ADC_WCLK for Audio Interface
1100: GPIO4/DIGMIC_DATA output is secondary bit-clock for Audio Interface
1101: GPIO4/DIGMIC_DATA output is secondary word-clock for Audio Interface
1110: GPIO4/DIGMIC_DATA output is clock for the digital microphone
1111: Reserved
D1
R
X
GPIO4/DIGMIC_DATA Input Pin state as a GPI
D0
R/W
0
GPIO4/DIGMIC_DATA as general purpose output control
0: GPIO4/DIGMIC_DATA pin is driven to '0' in general purpose output mode
1: GPIO4/DIGMIC_DATA pin is driven to '1' in general purpose output mode
6.2.116 Page 0 / Register 124:
GPIO5/DSD_CLK Control Register
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D6
R
00
Reserved. Write only default values
D5–D2
R/W
00 00
GPIO5/DSD_CLK Control
0000: GPIO5/DSD_CLK input/output disabled
0001: GPIO5/DSD_CLK input is used for secondary BCLK, secondary WCLK, secondary DIN or
secondary ADC_WCLK input
0010: GPIO5/DSD_CLK is general purpose input (GPI)
0011: GPIO5/DSD_CLK is general purpose output
0100: GPIO5/DSD_CLK output is CLKOUT
0101: GPIO5/DSD_CLK output is INT1 (active high)
0110: GPIO5/DSD_CLK output is inverted INT1 (active low)
0111: GPIO5/DSD_CLK output is INT1 (open drain)
1000: GPIO5/DSD_CLK output is INT2 (active high)
1001: GPIO5/DSD_CLK output is inverted INT2 (active low)
1010: GPIO5/DSD_CLK output is INT2 (open drain)
1011: GPIO5/DSD_CLK output is ADC_WCLK for Audio Interface
1100: GPIO5/DSD_CLK output is secondary bit-clock for Audio Interface
1101: GPIO5/DSD_CLK output is secondary word-clock for Audio Interface
1110: GPIO5/DSD_CLK output is clock for the digital microphone
1111: GPIO5/DSD_CLK output is the DAC modulator clock (DSD_CLK)
D1
R
X
GPIO5/DSD_CLK Input Pin state as a GPI
D0
R/W
0
GPIO5/DSD_CLK as general purpose output control
0: GPIO5/DSD_CLK pin is driven to '0' in general purpose output mode
1: GPIO5/DSD_CLK pin is driven to '1' in general purpose output mode
6.2.117 Page 0 / Register 125:
GPIO6/DSD_DATA Control Register
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D6
R
00
Reserved. Write only default values
120
REGISTER MAP
Copyright 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): TLV320AIC36
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