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參數資料
| 型號： | TMP90C400 |
| 廠商： | Toshiba Corporation |
| 元件分類： | 通用總線功能 |
| 英文描述： | High Speed Advanced CMOS 8-bit Microcontroller,Integrating 8-Bit CPU,RAM，ROM，General Serial Interface,Multifunction Timer/Event Counter(高速、先進的 CMOS 8位微控制器（芯片集成了8位CPU,ROM，RAM，通用串行接口，多功能定時器/事件計數器）) |
| 中文描述： | 采用先進的CMOS高速8位微控制器，集成8位CPU，內存，光盤，通用串行接口，多功能定時器/事件計數器（高速，先進的的CMOS 8位微控制器（芯片集成了8位的CPU，ROM和RAM內存，通用串行接口，多功能定時器/事件計數器）） |
| 文件頁數： | 28/100頁 |
| 文件大?。?/td> | 2591K |
| 代理商： | TMP90C400 |
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TOSHIBA CORPORATION
TMP90C400/401
3.4.3 IDLE 2 Mode
Figure 3.4 (2) shows the timing of HALT release caused by
interrupts in the RUN/IDLE 2 mode.
In the IDLE 2 mode, the halt state is released by an interrupt
with the same timing as in the RUN mode, except the internal
operation of the MCU. In the RUN mode, only the CPU stops
executing the current instruction, and the system clock is supplied
to all internal devices. In the IDLE 2 mode, however, the system
clock is supplied to only specific internal I/O devices. As a
result, the halt state in the IDLE 2 mode requires only a 1/3 of
the power consumed in the RUN mode. In the IDLE 2 mode,
the system clock is supplied to the following I/O devices:
8-bit timer
Serial interface
Note: Interrupt requests by external interrupts (INT0, INT1)
are prohibited through the HALT period in this mode.
3.4.4 STOP Mode
The STOP mode is selected to stop all internal circuits
including the internal oscillator. In this mode, all pins except
special pins are put in the high-impedance state, independent
of the internal operation of the MCU.
All interrupt request are prohibited through the HALT
period in this mode. (Note: that the external non-maskable
interrupt pin (NMI) should be kept as “1”.) By resetting, this
mode can be cleared. However programmable pull-up resistor
port remains as pulled up.
Table 3.4 (1) summarizes the state of these pins in the
STOP mode. Note, however, that the pre-halt state (The status
prior to execution of HALT instruction) of all output pins can be
retained by setting the internal I/O register STBMOD <DRIVE
(drive enable: bit 0 of memory address FF8FH) to “1”. The
content of this register is initialized to “0” by resetting.
The internal oscillator can also be restarted by the input of
the RESET signal at “0” to the CPU. In the Reset restart mode,
however, the normal operation may not be performed in order to
get the quick response of MCU when the power is turned on
(Power on Reset). It is due to the unstable clock supplied
immediately after restarting the internal oscillator. To avoid
this, it is necessary to keep the RESET signal at “0" long
enough to release the HALT state in the STOP mode.
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| TMP90CH03 | High Speed Advanced CMOS 8-bit Microcontroller,Integrating 8-Bit CPU,RAM，ROM，General Serial Interface,Timer/Event Counter(高速、先進的 CMOS 8位微控制器（芯片集成了8位CPU,ROM，RAM，通用串行接口，定時器/事件計數器）) |
相關代理商/技術參數 |
參數描述 |
|---|---|
| TMP90C400F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
| TMP90C400N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
| TMP90C400N/F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| TMP90C401F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
| TMP90C401N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
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