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參數(shù)資料
| 型號(hào)： | TMS320C15-25 |
| 廠(chǎng)商： | Texas Instruments, Inc. |
| 元件分類(lèi)： | 數(shù)字信號(hào)處理 |
| 英文描述： | Digital Signal Processors(160ns指令周期，分離的程序和數(shù)據(jù)總線(xiàn)，外部輪詢(xún)中斷的DSP) |
| 中文描述： | 數(shù)字信號(hào)處理器（160ns指令周期，分離的程序和數(shù)據(jù)總線(xiàn)，外部輪詢(xún)中斷的數(shù)字信號(hào)處理器） |
| 文件頁(yè)數(shù)： | 33/139頁(yè) |
| 文件大?。?/td> | 1478K |
| 代理商： | TMS320C15-25 |
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TMS320C14, TMS320E14, TMS320P14
DIGITAL SIGNAL PROCESSORS
SPRS009C–JANUARY 1987–REVISED JULY 1991
POST OFFICE BOX 1443
HOUSTON, TEXAS 77001
33
The accumulator stores the output from the ALU and is often an input to the ALU. It operates with a 32-bit
wordlength. The accumulator is divided into a high-order word (bits 31 through 16) and a low-order word (bits
15 through 0). Instructions are provided for storing the high- and low- order accumulator words in memory.
shifters
Two shifters are available for manipulating data. The ALU barrel shifter performs a left-shift of 0 to16 places on
data memory words loaded into the ALU. This shifter extends the high-order bit of the data word and zero-fills
the low-order bits for twos-complement arithmetic. The accumulator parallel shifter performs a left-shift of 0, 1,
or 4 places on the entire accumulator and places the resulting high-order accumulator bits into data RAM. Both
shifters are useful for scaling and bit extraction
16
×
16-bit parallel multiplier
The multiplier performs a 16
×
16-bit twos-complement multiplication with a 32-bit result in a single instruction
cycle. The multiplier consists of three units: the T Register, P Register, and the multiplier array. The 16-bit T
Register temporarily stores the multiplicand; the P Register stores the 32-bit product. Multiplier values either
come from the data memory or are derived immediately from the MPYK (multiply immediate) instruction word.
The fast on-chip multiplier allows the device to perform fundamental operations such as convolution, correlation,
and filtering.
data and program memory
Since the
′
C14/E14/P14 devices use a Harvard architecture, data and program memory reside in two separate
spaces. These devices have 256 words of on-chip data RAM and 4K words of on-chip program ROM (
′
C14)
or EPROM (
′
E14 and the OTP
′
P14). The EPROM cell utilizes standard PROM programmers and is
programmed identically to a 64K-bit CMOS EPROM (TMS27C64).
program memory expansion
The
′
C1x devices are capable of executing up to 4K words of external memory at full speed for those applications
requiring external program memory space. This allows for external RAM-based systems to provide multiple
functionality.
microcomputer/microprocessor operating modes
The
′
C14/E14/P14 devices offer two modes of operation defined by the state of the NMI/MC/MP pin during reset:
the microcomputer mode (NMI/MC/MP is high) or the microprocessor mode (NMI/MC/MP is low). In the
microcomputer mode, the on-chip ROM is mapped into the program memory space. In the microprocessor
mode, all 4K words of memory are external.
interrupts and subroutines
The
′
C14/E14/P14 devices contain a four-level hardware stack for saving the contents of the program counter
during interrupts and subroutine calls. Instructions are available for saving the complete context of the device.
PUSH and POP instructions permit a level of nesting restricted only by the amount of available RAM. The
′
C14/E14/P14 have a total of 15 internal/external interrupts. Fourteen of these are maskable; NMI is the
fifteenth.
input/output
The 16-bit parallel data bus can be utilized to access external peripherals. However, only the lower three address
lines are active. The upper nine address lines are driven high.
bit I/O
The
′
C14/E14/P14 has 16 pins of bit I/O that can be individually configured as inputs or outputs. Each of the
pins can be set or cleared without affecting the others. The input pins can also detect and match patterns and
generate a maskable interrupt signal to the CPU.
serial port
The
′
C14/E14/P14 includes an I/O-mapped asynchronous serial port.
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