參數(shù)資料
型號： TMS320C15-25
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： Digital Signal Processors(160ns指令周期，分離的程序和數(shù)據(jù)總線，外部輪詢中斷的DSP)
中文描述： 數(shù)字信號處理器（160ns指令周期，分離的程序和數(shù)據(jù)總線，外部輪詢中斷的數(shù)字信號處理器）
文件頁數(shù)： 9/139頁
文件大?。?/td> 1478K
代理商： TMS320C15-25
BRANCH ADDRESS
D
BRANCH ADDRESS
BRANCH ADDRESS
BRANCH ADDRESS
BRANCH ADDRESS
BRANCH ADDRESS
BRANCH ADDRESS
BRANCH ADDRESS
BRANCH ADDRESS
BRANCH ADDRESS
BRANCH ADDRESS
D
D
D
K
B
Branch unconditionally
2
2
BANZ
Branch on auxiliary register not zero
2
2
BGEZ
Branch if accumulator
≥
0
2
2
BGZ
Branch if accumulator > 0
2
2
BIOZ
Branch on BIO = 0
2
2
BLEZ
Branch if accumulator
≤
0
2
2
BLZ
Branch if accumulator < 0
2
2
BNZ
Branch if accumulator
≠
0
2
2
BV
Branch on overflow
2
2
BZ
Branch if accumulator = 0
2
2
CALA
Call subroutine from accumulator
CALL
Call subroutine immediately
2
2
RET
Return from subroutine or interrupt routine
NO.
CYCLES
NO.
CYCLES
NO.
WORDS
NO.
WORDS
SPRS009C–JANUARY 1987–REVISED JULY 1991
TMS320C1x
DIGITAL SIGNAL PROCESSORS
POST OFFICE BOX 1443
HOUSTON, TEXAS 77001
9
Table 3. TMS320C1x Instruction Set Summary (continued)
BRANCH INSTRUCTIONS
OPCODE
MNEMONIC
DESCRIPTION
INSTRUCTION REGISTER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
1
1
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
2
1
0
1
1
1
1
1
1
1
1
0
0
0
1
1
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
1
0
1
1
1
1
1
1
1
1
0
0
0
1
1
0
1
T REGISTER, P REGISTER, AND MULTIPLY INSTRUCTIONS
OPCODE
MNEMONIC
DESCRIPTION
INSTRUCTION REGISTER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
APAC
Add P register to accumulator
1
1
0
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
LT
Load T Register
1
1
0
1
1
0
1
0
1
0
M
LTA
LTA combines LT and APAC into one instruction
1
1
0
1
1
0
1
1
0
0
M
LTD
LTD combines LT, APAC, and DMOV into one instruction
1
1
0
1
1
0
1
0
1
1
M
MPY
Multiply with T register, store product in P register
1
1
0
1
1
0
1
1
0
1
M
MPYK
Multiply T register with immediate operand; store product
in P register
1
1
1
0
0
PAC
Load accumulator from P register
1
1
0
1
1
1
1
1
1
1
1
0
0
0
1
1
1
0
SPAC
Subtract P register from accumulator
1
1
0
1
1
1
1
1
1
1
1
0
0
1
0
0
0
0
This instruction is a NOP on the
′
320C14/E14/P14.
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