參數(shù)資料
型號(hào)： TMS320C240PQQ
英文描述： 16-Bit Microcontroller
中文描述： 16位微控制器
文件頁(yè)數(shù)： 10/105頁(yè)
文件大?。?/td> 1481K
代理商： TMS320C240PQQ
TMS320C240, TMS320F240
DSP CONTROLLERS
SPRS042D – OCTOBER 1996 – REVISED NOVEMBER 1998
10
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
Terminal Functions (Continued)
TERMINAL
NAME
TYPE
DESCRIPTION
NO.
SUPPLY SIGNALS
CVSS
8
I
Digital core logic ground reference
VSS
3
14
20
29
46
59
61
71
92
104
113
120
I
Digital logic ground reference
VSSA
87
I
Analog ground reference
DVDD
2
13
21
47
62
93
103
121
I
Digital I/O logic supply voltage
CVDD
7
I
Digital core logic supply voltage
60
VCCA
VREFHI
VREFLO
84
I
Analog supply voltage
85
I
ADC analog voltage reference high
86
I
ADC analog voltage reference low
TEST SIGNALS
TCK
30
I
IEEE standard test clock. TCK is normally a free-running clock signal with a 50% duty cycle. The
changes on test-access port (TAP) input signals (TMS and TDI) are clocked into the TAP controller,
instruction register, or selected test data register of the ’C2xx core on the rising edge of TCK. Changes
at the TAP output signal (TDO) occur on the falling edge of TCK.
TDI
31
I
IEEE standard test data input (TDI). TDI is clocked into the selected register (instruction or data) on
a rising edge of TCK.
TDO
34
O/Z
IEEE standard test data output (TDO). The contents of the selected register (instruction or data) are
shifted out of TDO on the falling edge of TCK. TDO is in the high-impedance state when OFF is active
low.
TMS
33
I
IEEE standard test mode select. This serial control input is clocked into the TAP controller on the rising
edge of TCK.
I = input, O = output, Z = high impedance
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