
TMS320C240, TMS320F240
DSP CONTROLLERS
SPRS042D – OCTOBER 1996 – REVISED NOVEMBER 1998
97
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
register file compilation
Table 20 is a collection of all the programmable registers of the TMS320x240 (provided for a quick reference).
Table 20. Register File Compilation
ADDR
BIT 15
BIT 14
BIT 13
BIT 12
BIT 11
BIT 10
BIT 9
BIT 8
REG
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
DATA MEMORY SPACE
CPU STATUS REGISTERS
ARP
OV
OVM
1
INTM
DP(8)
ST0
DP(7)
DP(6)
DP(5)
DP(4)
DP(3)
DP(2)
DP(1)
DP(0)
ARB
CNF
TC
SXM
C
1
ST1
1
1
1
XF
1
1
PM
GLOBAL MEMORY AND CPU INTERRUPT REGISTERS
00004h
—
—
—
—
—
—
—
—
IMR
—
—
INT6 MASK
INT5 MASK
INT4 MASK
INT3 MASK
INT2 MASK
INT1 MASK
00005h
—
—
—
—
—
—
—
—
GREG
Global Data Memory Configuration Bits (7–0)
00006h
—
—
—
—
—
—
—
—
IFR
—
—
INT6 FLAG
INT5 FLAG
INT4 FLAG
INT3 FLAG
INT2 FLAG
INT1 FLAG
SYSTEM CONFIGURATION REGISTERS
07018h
RESET1
RESET0
—
—
—
—
—
—
SYSCR
CLKSRC1
CLKSRC0
—
—
—
—
—
—
07019h
Reserved
0701Ah
PORST
—
—
ILLADR
—
SWRST
WDRST
—
SYSSR
—
—
HPO
—
VCCAOR
—
—
VECRD
0701Bh
to
0701Dh
Reserved
0701Eh
0
0
0
0
0
0
0
0
SYSIVR
D7
D6
D5
D4
D3
D2
D1
D0
0701Fh
Reserved
WD/RTI CONTROL REGISTERS
07020h
Reserved
07021h
D7
D6
D5
D4
D3
D2
D1
D0
RTICNTR
07022h
Reserved
07023h
D7
D6
D5
D4
D3
D2
D1
D0
WDCNTR
07024h
Reserved
07025h
D7
D6
D5
D4
D3
D2
D1
D0
WDKEY
07026h
Reserved
07027h
RTI FLAG
RTI ENA
—
—
—
RTIPS2
RTIPS1
RTIPS0
RTICR
07028h
Reserved
07029h
WD FLAG
WDDIS
WDCHK2
WDCHK1
WDCHK0
WDPS2
WDPS1
WDPS0
WDCR
PLL CLOCK CONTROL REGISTERS
0702Ah
Reserved
0702Bh
CLKMD(1)
CLKMD(0)
PLLOCK(1)
PLLOCK(0)
PLLPM(1)
PLLPM(0)
ACLKENA
PLLPS
CKCR0
0702Ch
Reserved