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參數(shù)資料
| 型號(hào)： | TMS320C240PQQ |
| 英文描述： | 16-Bit Microcontroller |
| 中文描述： | 16位微控制器 |
| 文件頁數(shù)： | 43/105頁 |
| 文件大小： | 1481K |
| 代理商： | TMS320C240PQQ |
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TMS320C240, TMS320F240
DSP CONTROLLERS
SPRS042D – OCTOBER 1996 – REVISED NOVEMBER 1998
43
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
capture unit (continued)
The capture unit includes the following features:
–
One 16-bit capture-control register, CAPCON, for reads or writes
–
One 16-bit capture-FIFO status register, CAPFIFO, with eight MSBs for read-only operations, and eight
LSBs for write-only operations
–
Optional selection of GP timer 2 and/or GP timer 3 through two 16-bit multiplexers (MUXs). One MUX
selects a GP timer for capture circuits 3 and 4, and the other MUX selects a GP timer for capture
circuits 1 and 2.
–
Four 16 bit x 2 FIFO stack registers, one two-level FIFO stack register per capture circuit. The top
register of each stack is a read-only register, FIFOx, where x = 1, 2, 3, or 4.
–
Four possible Schmitt-triggered capture-input pins (CAPx, x = 1 to 4) with one input pin per capture unit
–
The input pins CAP1 and CAP2 also can be used as inputs to the QEP circuit.
–
User-specified edge-detection mode at the input pins
–
Four maskable interrupts/flags, CAPINTx, where x = 1, 2, 3, or 4
quadrature-encoder pulse (QEP) circuit
Two capture inputs (CAP1 and CAP2) can be used to interface the on-chip QEP circuit with a quadrature
encoder pulse. Full synchronization of these inputs is performed on-chip. Direction or leading-quadrature pulse
sequence is detected, and GP timer 2 or 3 is incremented or decremented by the rising and falling edges of the
two input signals (four times the frequency of either input pulse).
analog-to-digital converter (ADC) module
A simplified functional block diagram of the ADC module is shown in Figure 12. The ADC module consists of
two 10-bit ADCs with two built-in sample-and-hold (S/H) circuits. A total of 16 analog input channels is available
on the TMS320x240. Eight analog inputs are provided for each ADC unit by way of an 8-to-1 analog multiplexer.
Minimum total conversion time for each ADC unit is 6.1 s. Total accuracy for each converter is
±
1.5 LSB.
Reference voltage for the ADC module needs to be supplied externally through the two reference pins, V
REFHI
and V
REFLO.
The digital result is expressed as:
Digital result = 1023 x Input Voltage
V
REFHI
– V
REFLO
Functions of the ADC module include:
Two input channels (one for each ADC unit) that can be sampled and converted simultaneously
Each ADC unit can perform single or continuous S/H and conversion operations.
Two 2-level-deep FIFO result registers for ADC units 1 and 2
ADC module (both A/D converters) can start operation by software instruction, external signal transition on
a device pin, or by event-manager events on each of the GP timer/compare output and the
capture 4 pins.
The ADC control register is double-buffered (with shadow register) and can be written to at any time. A new
conversion of ADC can start immediately or when the previous conversion process is completed according
to the control register bits.
At the end of each conversion, an interrupt flag is set and an interrupt is generated if it is unmasked/enabled.
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