參數(shù)資料
型號(hào)： TMS320C240PQQ
英文描述： 16-Bit Microcontroller
中文描述： 16位微控制器
文件頁數(shù)： 68/105頁
文件大?。?/td> 1481K
代理商： TMS320C240PQQ
TMS320C240, TMS320F240
DSP CONTROLLERS
SPRS042D – OCTOBER 1996 – REVISED NOVEMBER 1998
68
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
switching characteristics over recommended operating conditions [H = 0.5 t
c(CO)
] (see Figure 22)
PARAMETER
CLOCK MODE
MIN
TYP
MAX
UNIT
before PLL lock,
CLKIN divide by 2
2tc(Cl)
tc(CPU)
Cycle time, CPUCLK
before PLL lock,
CLKIN divide by 1
tc(Cl)
ns
after PLL lock
50
t(SYS)
tc(SYS)
Cycle time SYSCLK
Cycle time, SYSCLK
CPUCLK divide by 2
CPUCLK divide by 4
2tc(CPU)
4tc(CPU)
ns
tc(CO)
tf(CO)
tr(CO)
tw(COL)
tw(COH)
Cycle time, CLKOUT
50
ns
Fall time, CLKOUT
5
ns
Rise time, CLKOUT
5
ns
Pulse duration, CLKOUT low
H–10
H–6
H–1
ns
Pulse duration, CLKOUT high
H+0
H+4
H+8
ns
tp
Transition time, PLL synchronized after
PLL enabled
before PLL lock,
CLKIN divide by 2
2000tc(Cl)
ns
before PLL lock,
CLKIN divide by 1
1000tc(Cl)
This device utilizes a fully static design and, therefore, can operate with input clock cycle time [tc(CI)] approaching infinity. The device is
characterized at frequencies approaching 0 Hz.
SYSCLK is initialized to divide-by-4 mode by any device reset.
timing requirements over recommended operating conditions (see Note 1 and Figure 22)
EXTERNAL REFERENCE
CRYSTAL
MIN
MAX
UNIT
4 MHz
250
tc(Cl)
Cycle time, XTAL1/CLKIN
6 MHz
167
ns
8 MHz
125
tf(Cl)
tr(Cl)
tw(CIL)
tw(CIH)
This device utilizes a fully static design and, therefore, can operate with input clock cycle time [tc(CI)] approaching infinity. The device is
characterized at frequencies approaching 0 Hz.
NOTE 1: Timings assume CLKOUT is set to output CPUCLK. CLKOUT is initialized to CPUCLK by power-on reset.
Fall time, XTAL1/CLKIN
5
ns
Rise time, XTAL1/CLKIN
5
ns
Pulse duration, XTAL1/CLKIN low as a percentage of tc(CI)
Pulse duration, XTAL1/CLKIN high as a percentage of tc(CI)
40
60
%
40
60
%
XTAL1/CLKIN
tc(CI)
tw(CIL)
tw(CIH)
tw(COL)
tw(COH)
tc(CO)
tf(Cl)
tr(Cl)
tr(CO)
tf(CO)
CLKOUT
Figure 22. CLKIN-to-CLKOUT Timings for PLL Oscillator Mode, Multiply-by-5 Option With 4-MHz Crystal
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