參數(shù)資料
型號(hào): TMS320C6205GHK200
廠商: Texas Instruments
文件頁(yè)數(shù): 30/73頁(yè)
文件大小: 0K
描述: IC DSP FIXED POINT HP 288-BGA
標(biāo)準(zhǔn)包裝: 90
系列: TMS320C62x
類型: 定點(diǎn)
接口: McBSP,PCI
時(shí)鐘速率: 200MHz
非易失內(nèi)存: 外部
芯片上RAM: 128kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.50V
工作溫度: 0°C ~ 90°C
安裝類型: 表面貼裝
封裝/外殼: 288-LFBGA
供應(yīng)商設(shè)備封裝: 288-BGA Microstar(16x16)
包裝: 托盤
其它名稱: 296-12673
TMS320C6205
FIXEDPOINT DIGITAL SIGNAL PROCESSOR
SPRS106G OCTOBER 1999 REVISED JULY 2006
36
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
INPUT AND OUTPUT CLOCKS
timing requirements for CLKIN§ (see Figure 12)
200
NO.
PLL mode x4,
x6, x7, x8, x9,
x10, x11
PLL mode
x1
UNIT
MIN
MAX
MIN
MAX
1
tc(CLKIN)
Cycle time, CLKIN
5 * M
5
ns
2
tw(CLKINH) Pulse duration, CLKIN high
0.4C
0.45C
ns
3
tw(CLKINL)
Pulse duration, CLKIN low
0.4C
0.45C
ns
4
tt(CLKIN)
Transition time, CLKIN
5
0.6
ns
The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
M = the PLL multiplier factor (x4, x6, x7, x8, x9, x10, or x11). For more details, see the clock PLL section of this data sheet.
§ C = CLKIN cycle time in ns. For example, when CLKIN frequency is 50 MHz, use C = 20 ns.
CLKIN
1
2
3
4
Figure 12. CLKIN Timings
timing requirements for PCLKIN (see Figure 13)
NO.
200
UNIT
NO.
MIN
MAX
UNIT
1
tc(PCLK)
Cycle time, PCLK
30
ns
2
tw(PCLKH)
Pulse duration, PCLK high
11
ns
3
tw(PCLKL)
Pulse duration, PCLK low
11
ns
4
tsr(PCLK)
v/t slew rate, PCLK
1
4
V/ns
When the 5-V PCI clamp is used, the reference points for the rise and fall transitions are measured VILP MAX and VIHP MIN for 5 V operation.
When the 3.3-V PCI clamp is used, the reference points for the rise and fall transitions are measured at VILP MAX and VIHP MIN for 3.3 V
operation.
PCLK
1
2
3
4
2 V MIN
Peak to Peak for
5V signaling
or
0.4 VIOP MIN
Peak to Peak for
3V signaling
Figure 13. PCLK Timings
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