參數(shù)資料
型號: TMS320C6205GHK200
廠商: Texas Instruments
文件頁數(shù): 36/73頁
文件大?。?/td> 0K
描述: IC DSP FIXED POINT HP 288-BGA
標準包裝: 90
系列: TMS320C62x
類型: 定點
接口: McBSP,PCI
時鐘速率: 200MHz
非易失內存: 外部
芯片上RAM: 128kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.50V
工作溫度: 0°C ~ 90°C
安裝類型: 表面貼裝
封裝/外殼: 288-LFBGA
供應商設備封裝: 288-BGA Microstar(16x16)
包裝: 托盤
其它名稱: 296-12673
TMS320C6205
FIXEDPOINT DIGITAL SIGNAL PROCESSOR
SPRS106G OCTOBER 1999 REVISED JULY 2006
41
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
SYNCHRONOUS-BURST MEMORY TIMING
timing requirements for synchronous-burst SRAM cycles (see Figure 19)
NO.
200
UNIT
NO.
MIN
MAX
UNIT
7
tsu(EDV-CKO2H)
Setup time, read EDx valid before CLKOUT2 high
2.5
ns
8
th(CKO2H-EDV)
Hold time, read EDx valid after CLKOUT2 high
1.5
ns
switching characteristics over recommended operating conditions for synchronous-burst SRAM
cycles (see Figure 19 and Figure 20)
NO.
PARAMETER
200
UNIT
NO.
PARAMETER
MIN
MAX
UNIT
1
tosu(CEV-CKO2H)
Output setup time, CEx valid before CLKOUT2 high
P 0.8
ns
2
toh(CKO2H-CEV)
Output hold time, CEx valid after CLKOUT2 high
P 4
ns
3
tosu(BEV-CKO2H)
Output setup time, BEx valid before CLKOUT2 high
P 0.8
ns
4
toh(CKO2H-BEIV)
Output hold time, BEx invalid after CLKOUT2 high
P 4
ns
5
tosu(EAV-CKO2H)
Output setup time, EAx valid before CLKOUT2 high
P 0.8
ns
6
toh(CKO2H-EAIV)
Output hold time, EAx invalid after CLKOUT2 high
P 4
ns
9
tosu(ADSV-CKO2H)
Output setup time, SDCAS/SSADS valid before CLKOUT2 high
P 0.8
ns
10
toh(CKO2H-ADSV)
Output hold time, SDCAS/SSADS valid after CLKOUT2 high
P 4
ns
11
tosu(OEV-CKO2H)
Output setup time, SDRAS/SSOE valid before CLKOUT2 high
P 0.8
ns
12
toh(CKO2H-OEV)
Output hold time, SDRAS/SSOE valid after CLKOUT2 high
P 4
ns
13
tosu(EDV-CKO2H)
Output setup time, EDx valid before CLKOUT2 high§
P 1
ns
14
toh(CKO2H-EDIV)
Output hold time, EDx invalid after CLKOUT2 high
P 4
ns
15
tosu(WEV-CKO2H)
Output setup time, SDWE/SSWE valid before CLKOUT2 high
P 0.8
ns
16
toh(CKO2H-WEV)
Output hold time, SDWE/SSWE valid after CLKOUT2 high
P 4
ns
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM accesses.
§ For the first write in a series of one or more consecutive adjacent writes, the write data is generated one CLKOUT2 cycle early to accommodate
the ED enable time.
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