參數資料
型號： TMS320C6415TGLZ7
廠商： Texas Instruments
文件頁數： 141/146頁
文件大?。?/td> 0K
描述： IC DSP FIXED-POINT 532-FCBGA
標準包裝： 60
系列： TMS320C6414T/15T/16T
類型： 定點
接口： 主機接口，McBSP，PCI，UTOPIA
時鐘速率： 720MHz
非易失內存： 外部
芯片上RAM： 1.03MB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.20V
工作溫度： 0°C ~ 90°C
安裝類型： 表面貼裝
封裝/外殼： 532-BFBGA，FCBGA
供應商設備封裝： 532-FCBGA（23x23）
包裝： 托盤
配用： TMDXEVM6452-ND - TMDXEVM6452
296-23038-ND - DSP STARTER KIT FOR TMS320C6416
其它名稱： 296-17756
TMS320C6414T, TMS320C6415T, TMS320C6416T
FIXEDPOINT DIGITAL SIGNAL PROCESSORS
SPRS226M NOVEMBER 2003 REVISED APRIL 2009
94
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
SYNCHRONOUS DRAM TIMING
timing requirements for synchronous DRAM cycles for EMIFA module (see Figure 27)
NO.
600
720
850
1G
UNIT
MIN
MAX
6
tsu(EDV-EKO1H)
Setup time, read EDx valid before ECLKOUTx high
0.6
ns
7
th(EKO1H-EDV)
Hold time, read EDx valid after ECLKOUTx high
CVDD = 1.2 V
1.8
ns
7
th(EKO1H-EDV)
Hold time, read EDx valid after ECLKOUTx high
CVDD = 1.1 V
2.0
ns
These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a
“B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the synchronous DRAM
memory access signals are shown as generic ( SDCAS, SDWE, and SDRAS ) instead of ASDCAS, ASDWE, and ASDRAS (for EMIFA) and
BSDCAS, BSDWE, and BSDRAS (for EMIFB)].
switching characteristics over recommended operating conditions for synchronous DRAM cycles
for EMIFA module (see Figure 27Figure 34)
NO.
PARAMETER
600
720
850
1G
UNIT
MIN
MAX
1
td(EKO1H-CEV)
Delay time, ECLKOUTx high to CEx valid
1.3
4.9
ns
2
td(EKO1H-BEV)
Delay time, ECLKOUTx high to BEx valid
4.9
ns
3
td(EKO1H-BEIV)
Delay time, ECLKOUTx high to BEx invalid
1.3
ns
4
td(EKO1H-EAV)
Delay time, ECLKOUTx high to EAx valid
4.9
ns
5
td(EKO1H-EAIV)
Delay time, ECLKOUTx high to EAx invalid
1.3
ns
8
td(EKO1H-CASV)
Delay time, ECLKOUTx high to SDCAS valid
1.3
4.9
ns
9
td(EKO1H-EDV)
Delay time, ECLKOUTx high to EDx valid
4.9
ns
10
td(EKO1H-EDIV)
Delay time, ECLKOUTx high to EDx invalid
1.3
ns
11
td(EKO1H-WEV)
Delay time, ECLKOUTx high to SDWE valid
1.3
4.9
ns
12
td(EKO1H-RAS)
Delay time, ECLKOUTx high to SDRAS valid
1.3
4.9
ns
13
td(EKO1H-ACKEV)
Delay time, ECLKOUTx high to ASDCKE valid (EMIFA only)
1.3
4.9
ns
14
td(EKO1H-PDTV)
Delay time, ECLKOUTx high to PDT valid
1.3
4.9
ns
These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a
“B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the synchronous DRAM
memory access signals are shown as generic ( SDCAS, SDWE, and SDRAS ) instead of ASDCAS, ASDWE, and ASDRAS (for EMIFA) and
BSDCAS, BSDWE, and BSDRAS (for EMIFB)].
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