參數(shù)資料
型號: TMS320C6415TGLZ7
廠商: Texas Instruments
文件頁數(shù): 34/146頁
文件大?。?/td> 0K
描述: IC DSP FIXED-POINT 532-FCBGA
標(biāo)準(zhǔn)包裝: 60
系列: TMS320C6414T/15T/16T
類型: 定點(diǎn)
接口: 主機(jī)接口,McBSP,PCI,UTOPIA
時鐘速率: 720MHz
非易失內(nèi)存: 外部
芯片上RAM: 1.03MB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.20V
工作溫度: 0°C ~ 90°C
安裝類型: 表面貼裝
封裝/外殼: 532-BFBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 532-FCBGA(23x23)
包裝: 托盤
配用: TMDXEVM6452-ND - TMDXEVM6452
296-23038-ND - DSP STARTER KIT FOR TMS320C6416
其它名稱: 296-17756
TMS320C6414T, TMS320C6415T, TMS320C6416T
FIXEDPOINT DIGITAL SIGNAL PROCESSORS
SPRS226M NOVEMBER 2003 REVISED APRIL 2009
129
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
UTOPIA SLAVE TIMING [C6415T AND C6416T ONLY] (CONTINUED)
timing requirements for UTOPIA Slave transmit (see Figure 59)
NO.
600, 720
850, 1G
UNIT
NO.
MIN
MAX
UNIT
2
tsu(UXAV-UXCH)
Setup time, UXADDR valid before UXCLK high
4
ns
3
th(UXCH-UXAV)
Hold time, UXADDR valid after UXCLK high
1
ns
8
tsu(UXENBL-UXCH)
Setup time, UXENB low before UXCLK high
4
ns
9
th(UXCH-UXENBL)
Hold time, UXENB low after UXCLK high
1
ns
switching characteristics over recommended operating conditions for UTOPIA Slave transmit
(see Figure 59)
NO.
PARAMETER
600, 720
850, 1G
UNIT
NO.
PARAMETER
MIN
MAX
UNIT
1
td(UXCH-UXDV)
Delay time, UXCLK high to UXDATA valid
3
12
ns
4
td(UXCH-UXCLAV)
Delay time, UXCLK high to UXCLAV driven active value
3
12
ns
5
td(UXCH-UXCLAVL)
Delay time, UXCLK high to UXCLAV driven inactive low
3
12
ns
6
td(UXCH-UXCLAVHZ)
Delay time, UXCLK high to UXCLAV going Hi-Z
9
18.5
ns
7
tw(UXCLAVL-UXCLAVHZ)
Pulse duration (low), UXCLAV low to UXCLAV Hi-Z
3
ns
10
td(UXCH-UXSV)
Delay time, UXCLK high to UXSOC valid
3
12
ns
P47
P48
H1
N
0x1F
N
0x1F
N + 1
0x1F
N
10
8
4
3
2
1
UXCLK
UXDATA[7:0]
UXADDR[4:0]
UXCLAV
UXENB
UXSOC
9
P46
P45
0 x1F
The UTOPIA Slave module has signals that are middle-level signals indicating a high-impedance state (i.e., the UXCLAV and
UXSOC signals).
5
6
7
Figure 59. UTOPIA Slave Transmit Timing
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