參數(shù)資料
型號： TMS320C6415TGLZ7
廠商： Texas Instruments
文件頁數(shù)： 31/146頁
文件大?。?/td> 0K
描述： IC DSP FIXED-POINT 532-FCBGA
標準包裝： 60
系列： TMS320C6414T/15T/16T
類型： 定點
接口： 主機接口，McBSP，PCI，UTOPIA
時鐘速率： 720MHz
非易失內(nèi)存： 外部
芯片上RAM： 1.03MB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.20V
工作溫度： 0°C ~ 90°C
安裝類型： 表面貼裝
封裝/外殼： 532-BFBGA，F(xiàn)CBGA
供應商設備封裝： 532-FCBGA（23x23）
包裝： 托盤
配用： TMDXEVM6452-ND - TMDXEVM6452
296-23038-ND - DSP STARTER KIT FOR TMS320C6416
其它名稱： 296-17756
TMS320C6414T, TMS320C6415T, TMS320C6416T
FIXEDPOINT DIGITAL SIGNAL PROCESSORS
SPRS226M NOVEMBER 2003 REVISED APRIL 2009
126
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING (CONTINUED)
timing requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 (see Figure 56)
NO.
600
720
850
1G
UNIT
NO.
MASTER
SLAVE
UNIT
MIN
MAX
MIN
MAX
4
tsu(DRV-CKXH) Setup time, DR valid before CLKX high
12
2 12P
ns
5
th(CKXH-DRV)
Hold time, DR valid after CLKX high
4
5 + 24P
ns
P = 1/CPU clock frequency in ns. For example, when running parts at 720 MHz, use P = 1.39 ns.
For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics over recommended operating conditions for McBSP as SPI Master or
Slave: CLKSTP = 11b, CLKXP = 1 (see Figure 56)
NO.
PARAMETER
600
720
850
1G
UNIT
NO.
PARAMETER
MASTER§
SLAVE
UNIT
MIN
MAX
MIN
MAX
1
th(CKXH-FXL)
Hold time, FSX low after CLKX high
H 2
H + 3
ns
2
td(FXL-CKXL)
Delay time, FSX low to CLKX low#
T 2
T + 1
ns
3
td(CKXH-DXV)
Delay time, CLKX high to DX valid
2
4
12P + 2.8
20P + 17
ns
6
tdis(CKXH-DXHZ)
Disable time, DX high impedance following last data bit
from CLKX high
2
4
12P + 3
20P + 17
ns
7
td(FXL-DXV)
Delay time, FSX low to DX valid
L 2
L + 4
8P + 2
16P + 17
ns
P = 1/CPU clock frequency in ns. For example, when running parts at 720 MHz, use P = 1.39 ns.
For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
§ S = Sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency)
=
Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T =
CLKX period = (1 + CLKGDV) * S
H =
CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L =
CLKX low pulse width
= (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP
# FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock
(CLKX).
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