參數(shù)資料
型號: TMS320C6713BGDPA200
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號處理
英文描述: FLOATING-POINT DIGITAL SIGNAL PROCESSORS
中文描述: 浮點數(shù)字信號處理器
文件頁數(shù): 49/150頁
文件大?。?/td> 2039K
代理商: TMS320C6713BGDPA200
TMS320C6713, TMS320C6713B
FLOATING-POINT DIGITAL SIGNAL PROCESSORS
SPRS186I
DECEMBER 2001
REVISED MAY 2004
49
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
Terminal Functions (Continued)
SIGNAL
NAME
PIN NO.
PYP
TYPE
IPD/
IPU
DESCRIPTION
GDP
HOST-PORT INTERFACE (HPI) (CONTINUED)
Host-port data pin 6 (
I/O/Z
) [ default] or McASP1 receive high-frequency master
clock (I/O/Z).
IPU
clock (I/O/Z).
HD6/AHCLKR1
161
C17
I/O/Z
IPU
HD5/AHCLKX1
159
B18
Host-port data pin 5 (
I/O/Z
) [ default] or McASP1 transmit high-frequency master
HD4/GP[0]
156
C19
I/O/Z
IPD
Host-port data pin 4 (
I/O/Z
) [ default] or this pin can be programmed as a GP[0]
pin (I/O/Z).
HD3/AMUTE1
154
C20
IPU
Host-port data pin 3 (
I/O/Z
) [ default] or McASP1 mute output (O/Z).
Host-port data pin 2 (
I/O/Z
) [ default] or McASP1 transmit frame sync or left/right
clock (LRCLK) (I/O/Z).
HD2/AFSX1
155
D18
I/O/Z
IPU
HD1/AXR1[7]
HD0/AXR1[4]
HAS/ACLKX1
HCS/AXR1[2]
HDS1/AXR1[6]
HDS2/AXR1[5]
HRDY/ACLKR1
152
147
153
145
151
150
140
D20
E20
E18
F20
E19
F18
H19
IPU
IPU
IPU
IPU
IPU
IPU
IPD
Host-port data pin 1 (
I/O/Z
) [ default] or McASP1 data pin 7 (I/O/Z).
Host-port data pin 0 (
I/O/Z
) [ default] or McASP1 data pin 4 (I/O/Z).
Host address strobe (
I
) [default] or McASP1 transmit bit clock (I/O/Z).
Host chip select (
I
) [default] or McASP1 data pin 2 (I/O/Z).
Host data strobe 1 (
I
) [default] or McASP1 data pin 6 (I/O/Z).
Host data strobe 2 (
I
) [default] or McASP1 data pin 5 (I/O/Z) .
Host ready (from DSP to host) (
O
) [default] or McASP1 receive bit clock (I/O/Z).
EMIF
COMMON SIGNALS TO ALL TYPES OF MEMORY
O/Z
IPU
O/Z
IPU
O/Z
IPU
O/Z
IPU
O/Z
IPU
O/Z
IPU
O/Z
IPU
Byte-write enables for most types of memory
b di
tl
t d t SDRAM
O/Z
IPU
EMIF
BUS ARBITRATION
O/Z
IPU
Hold-request-acknowledge to the host
I
IPU
Hold request from the host
O/Z
IPU
Bus request output
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. [These IPD/IPU signal pins feature a 13-k
resistor (approximate) for the IPD or 18-k
resistor
(approximate) for the IPU. An external pullup or pulldown resistor no greater than 4.4 k
and 2.0 k
, respectively, should be used to pull a signal
to the opposite supply rail.]
To maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines.
I/O/Z
I
I
I
I
O/Z
CE3
CE2
CE1
CE0
BE3
BE2
BE1
BE0
57
61
103
102
108
110
V6
W6
W18
V17
V5
Y4
U19
V20
Memory space enables
Enabled by bits 28 through 31 of the word address
Only one asserted during any external data access
Byte-enable control
Decoded from the two lowest bits of the internal address
Can be directly connected to SDRAM read and write mask signal (SDQM)
it
k i
HOLDA
HOLD
BUSREQ
137
138
136
J18
J17
J19
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