TMS320C6713, TMS320C6713B
FLOATING-POINT DIGITAL SIGNAL PROCESSORS
SPRS186I
DECEMBER 2001
REVISED MAY 2004
85
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
multichannel audio serial port (McASP) peripherals (continued)
supported bit stream formats for TDM and burst transfer modes
The serial data pins support a wide variety of formats. In the TDM and burst synchronous modes, the data may
be transmitted / received with the following options:
Time slots per frame: 1 (Burst/Data Driven), or 2,3...32 (TDM/Time-Driven).
Time slot size: 8, 12, 16, 20, 24, 28, 32 bits per time slot
Data size: 8, 12, 16, 20, 24, 28, 32 bits (must be less than or equal to time slot)
Data alignment within time slot: Left- or Right-Justified
Bit order: MSB or LSB first.
Unused bits in time slot: Padded with 0, 1 or extended with value of another bit.
Time slot delay from frame sync: 0,1, or 2 bit delay
The data format can be programmed independently for transmit and receive, and for McASP0 vs. McASP1. In
addition, the McASP can automatically re-align the data as processed natively by the DSP (any format on a
nibble boundary) adjusting the data in hardware to any of the supported serial bit stream formats (TDM, Burst,
and DIT modes). This reduces the amount of bit manipulation that the DSP must perform and simplifies software
architecture.
digital audio interface transmitter (DIT) transfer mode (transmitter only)
The McASP transmit section may also be configured in digital audio interface transmitter (DIT) mode where it
outputs data formatted for transmission over an S/PDIF, AES-3, IEC-60958, or CP-430 standard link. These
standards encode the serial data such that the equivalent of ’clock’ and ’frame sync’ are embedded within the
data stream. DIT transfer mode is used as an interconnect between audio components and can transfer
multichannel digital audio data over a single optical or coaxial cable.
From an internal DSP standpoint, the McASP operation in DIT transfer mode is similar to the two time slot TDM
mode, but the data transmitted is output as a bi-phase mark encoded bit stream with preamble, channel status,
user data, validity, and parity automatically stuffed into the bit stream by the McASP module. The McASP
includes separate validity bits for even/odd subframes and two 384-bit register file modules to hold channel
status and user data bits.
DIT mode requires at minimum:
One serial data pin (if the AUXCLK is used as the reference [see the PLL and Clock Generator Logic
Figure 15]) or
One serial data pin plus either the AHCLKX or ACLKX pin (if an external clock is needed).
If additional serial data pins are used, each McASP may be used to transmit multiple encoded bit streams (one
per pin). However, the bit streams will all be synchronized to the same clock and the user data, channel status,
and validity information carried by each bit stream will be the same for all bit streams transmitted by the same
McASP module.
The McASP can also automatically re-align the data as processed by the DSP (any format on a nibble boundary)
in DIT mode; reducing the amount of bit manipulation that the DSP must perform and simplifies software
architecture.