參數(shù)資料
型號： TMS320C6713BGDPA200
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： FLOATING-POINT DIGITAL SIGNAL PROCESSORS
中文描述： 浮點數(shù)字信號處理器
文件頁數(shù)： 68/150頁
文件大?。?/td> 2039K
代理商： TMS320C6713BGDPA200
TMS320C6713, TMS320C6713B
FLOATING-POINT DIGITAL SIGNAL PROCESSORS
SPRS186I
DECEMBER 2001
REVISED MAY 2004
68
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
cache configuration (CCFG) register description (13B)
The C6713B device includes an enhancement to the
cache configuration (
CCFG) register. A “P” bit
(CCFG.31) allows the programmer to select the priority of accesses to L2 memory originating from the transfer
crossbar (TC) over accesses originating from the L1D memory system. An important class of TC accesses is
EDMA transfers, which move data to or from the L2 memory. While the EDMA normally has no issue accessing
L2 memory due to the high hit rates on the L1D memory system, there are pathological cases where certain
CPU behavior could block the EDMA from accessing the L2 memory for long enough to cause a missed deadline
when transferring data to a peripheral such as the McASP or McBSP. This can be avoided by setting the P bit
to “1” because the EDMA will assume a higher priority than the L1D memory system when accessing L2
memory.
For more detailed information on the P-bit function and for silicon advisories concerning EDMA L2 memory
accesses blocked, see the
TMS320C6713, TMS320C6713B Digital Signal Processors Silicon Errata
(literature
number SPRZ191).
31
30
10
9
8
7
3
2
0
P
Reserved
IP
ID
Reserved
L2MODE
R/W-0
R-x
W-0
W-0
R-0 0000
R/W-000
Legend:
R = Readable; R/W = Readable/Writeable; -
n
= value after reset; -x = undefined value after reset
Unlike the C6713 device, the C6713B device includes a P bit.
Figure 14.
Cache Configuration Register (CCFG)
Table 26. CCFG Register Bit Field Description
BIT #
NAME
DESCRIPTION
31
P
L1D requestor priority to L2 bit.
P = 0: L1D requests to L2 higher priority than TC requests
P =
1: TC requests to L2 higher priority than L1D requests
30:10
Reserved
Reserved. Read-only, writes have no effect.
Invalidate L1P bit.
0
= Normal L1P operation
1
=
All L1P lines are invalidated
9
IP
8
ID
Invalidate L1D bit.
0
= Normal L1D operation
1
=
All L1D lines are invalidated
7:3
Reserved
Reserved. Read-only, writes have no effect.
L2 operation mode bits (L2MODE).
2:0
L2MODE
000b =
001b =
010b =
011b =
111b
All others Reserved
L2 Cache disabled (All SRAM mode) [256K SRAM]
1-way Cache (16K L2 Cache) / [240K SRAM]
2-way Cache (32K L2 Cache) / [224K SRAM]
3-way Cache (48K L2 Cache) / [208K SRAM]
4-way Cache (64K L2 Cache) / [192K SRAM]
=
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TMS320C6713BGDP-C20 制造商:Texas Instruments 功能描述:
TMS320C6713BPYP167 制造商:TI 功能描述:_
TMS320C6713BPYP200 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC Floating-Pt Dig Sig Processors RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
TMS320C6713BPYP225 制造商:Texas Instruments 功能描述:
TMS320C6713BZDP225 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC Floating-Pt Dig Sig Processors RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
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