參數(shù)資料
型號： TMS320DM355_07
廠商： Texas Instruments, Inc.
英文描述： Digital Media System-on-Chip (DMSoC)
中文描述： 數(shù)字媒體系統(tǒng)芯片（DMSoC）
文件頁數(shù)： 20/158頁
文件大?。?/td> 1319K
代理商： TMS320DM355_07
www.ti.com
P
2.4.4
DDR Memory Interface
TMS320DM355
Digital Media System-on-Chip (DMSoC)
SPRS463B–SEPTEMBER 2007–REVISED OCTOBER 2007
Table 2-9. Asynchronous EMIF/NAND/OneNAND Terminal Functions (continued)
TERMINAL
TYPE
(1)
OTHER
(2)(3)
DESCRIPTION
NAME
NO.
Async EMIF: Lowest numbered chip select. Can be programmed to be used for
standard asynchronous memories (example: flash), OneNAND, or NAND
memory. Used for the default boot and ROM boot modes.
GIO: GIO[037]
Async EMIF: Second chip select. Can be programmed to be used for standard
asynchronous memories(example: flash), OneNAND, or NAND memory.
GIO: GIO[036]
Async EMIF: Write Enable
NAND/SM/xD: WE (Write Enable) output
GIO: GIO[035]
Async EMIF: Output Enable
NAND/SM/xD: RE (Read Enable) output
GIO: GIO[034]
Async EMIF: Async WAIT
NAND/SM/xD: RDY/ BSY input
GIO: GIO[033]
OneNAND: Address valid detect for OneNAND interface
GIO: GIO[032]
OneNAND: Clock for OneNAND flash interface
GIO: GIO[031]
EM_CE0/
GIO037
J16
I/O/Z
V
DD
EM_CE1/
GIO036
G19
I/O/Z
V
DD
EM_WE/
GIO035
J15
I/O/Z
V
DD
EM_OE/
GIO034
F19
I/O/Z
V
DD
EM_WAIT/
GIO033
G18
I/O/Z
V
DD
EM_ADV/
GIO032
EM_CLK/
GIO031
H16
I/O/Z
V
DD
E19
I/O/Z
V
DD
The DDR EMIF supports DDR2 and mobile DDR.
Table 2-10. DDR Terminal Functions
TERMINAL
TYPE
(1)
OTHER
(2)(3)
DESCRIPTION
NAME
DDR_CLK
DDR_CLK
DDR_RAS
DDR_CAS
DDR_WE
DDR_CS
DDR_CKE
DDR_DQM[
1]
DDR_DQM[
0]
DDR_DQS[
1]
NO.
W9
W8
T6
V9
W10
T8
V10
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
V
DD_DDR
V
DD_DDR
V
DD_DDR
V
DD_DDR
V
DD_DDR
V
DD_DDR
V
DD_DDR
DDR Data Clock
DDR Complementary Data Clock
DDR Row Address Strobe
DDR Column Address Strobe
DDR Write Enable
DDR Chip Select
DDR Clock Enable
Data mask outputs:
DQM0 - For DDR_DQ[7:0]
DQM1 - For DDR_DQ[15:8]
U15
I/O/Z
V
DD_DDR
T12
I/O/Z
V
DD_DDR
Data strobe input/outputs for each byte of the 16-bit data bus used to
synchronize the data transfers. Output to DDR when writing and inputs when
reading.
DQS1 - For DDR_DQ[15:8]
DQS0 - For DDR_DQ[7:0]
Bank select outputs. Two are required for 1Gb DDR2 memories.
Bank select outputs. Two are required for 1Gb DDR2 memories.
Bank select outputs. Two are required for 1Gb DDR2 memories.
DDR Address Bus bit 13
DDR Address Bus bit 12
DDR Address Bus bit 11
V15
I/O/Z
V
DD_DDR
DDR_DQS[
0]
V12
I/O/Z
V
DD_DDR
DDR_BA[2]
DDR_BA[1]
DDR_BA[0]
DDR_A13
DDR_A12
DDR_A11
V8
U7
U8
U6
V7
W7
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
V
DD_DDR
V
DD_DDR
V
DD_DDR
V
DD_DDR
V
DD_DDR
V
DD_DDR
(1)
(2)
(3)
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.
Specifies the operating I/O supply voltage for each signal. See
Section 5.3
,
Power Supplies
for more detail.
PD = pull-down, PU = pull-up. (To pull up a signal to the opposite supply rail, a 1 k
resistor should be used.)
Device Overview
20
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