參數(shù)資料
型號： TMS320DM355_07
廠商： Texas Instruments, Inc.
英文描述： Digital Media System-on-Chip (DMSoC)
中文描述： 數(shù)字媒體系統(tǒng)芯片（DMSoC）
文件頁數(shù)： 71/158頁
文件大?。?/td> 1319K
代理商： TMS320DM355_07
www.ti.com
P
3.5.4
Peripheral Clocking Considerations
TMS320DM355
Digital Media System-on-Chip (DMSoC)
SPRS463B–SEPTEMBER 2007–REVISED OCTOBER 2007
3.5.3.2.2
DM355-270 PLL2 (36 MHz reference)
All supported clocking configurations for DM355-270 PLL2 with 36 MHz reference clock are shown in
Table 3-5
Table 3-9. PLL2 Supported Clocking Configurations for DM355-270 (36 MHz reference)
PREDIV
PLLM
(m
POSTDIV
(/1 fixed)
PLL2 VCO
(MHz)
DDR PHY
DDR Clock
DDR_CLK
(MHz)
18
216
207
198
189
180
171
162
153
144
133
100
80
(/n programmable)
PLLDIV1
(/1 fixed)
1
1
1
1
1
1
1
1
1
1
1
1
1
SYSCLK1
(MHz)
36
432
414
396
378
360
342
324
306
288
266
200
160
programmable)
bypass
144
138
132
126
120
114
108
102
96
133
150
120
bypass
12
12
12
12
12
12
12
12
12
18
27
27
bypass
1
1
1
1
1
1
1
1
1
1
1
1
bypass
432
414
396
378
360
342
324
306
288
266
200
160
3.5.4.1
Video Processing Back End Clocking
The Video Processing Back End (VPBE) is a sub-module of the VPSS (Video Processing Subsystem).
The VPBE is designed to interface with a variety of LCDs and an internal DAC module. There are two
asynchronous clock domains in the VPBE: an internal clock domain and an external clock domain. The
internal clock domain is driven by the VPSS clock (PLL1 SYSCLK4). The external clock domain is
configurable; you can select one of five source:
24 MHz crystal input at MXI1
27 MHz crystal input at MXI2 (optional feature, not typically used)
PLL1 SYSCLK3
EXTCLK pin (external VPBE clock input pin)
PCLK pin (VPFE pixel clock input pin)
See the TMS320DM355 DMSoC Video Processing Back End (VPBE) User's Guide for complete
information on VPBE clocking.
3.5.4.2
USB Clocking
The USB Controller is driven by two clocks: an output clock of PLL1 (SYSCLK2) and an output clock of
the USB PHY.
NOTE
For proper USB 2.0 function, SYSCLK2 must be greater than 60 MHz.
The USB PHY takes an input clock that is configurable by the USB PHY clock source bits (PHYCLKSRC)
in the USB PHY control register (USB_PHY_CTL) in the System Control Module. When a 24 MHz crystal
is used at MXI1/MXO1, set PHYCLKSRC to 0. This will present a 24 MHz clock to the USB PHY. When a
36 MHz crystal is used at MXI1/MXO1, set PHYCLKSRC to 1. This will present a 12 MHz clock (36 MHz
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