參數(shù)資料
型號(hào)： TMS320F206PZL
元件分類： 數(shù)字信號(hào)處理
英文描述： 16-Bit Digital Signal Processor
中文描述： 16位數(shù)字信號(hào)處理器
文件頁(yè)數(shù)： 11/57頁(yè)
文件大?。?/td> 793K
代理商： TMS320F206PZL
TMS320F206
DIGITAL SIGNAL PROCESSOR
SPRS050A – NOVEMBER 1996 – REVISED APRIL 1998
11
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
status and control registers (continued)
Table 5. Status Register Field Definitions
FIELD
FUNCTION
ARB
Auxiliary register pointer buffer. Whenever the ARP is loaded, the old ARP value is copied to the ARB except during an LST
instruction. When the ARB is loaded by an LST #1 instruction, the same value is also copied to the ARP.
ARP
Auxiliary register pointer. ARP selects the AR to be used in indirect addressing. When the ARP is loaded, the old ARP value
is copied to the ARB register. ARP can be modified by memory-reference instructions when using indirect addressing, and by
the LARP, MAR, and LST instructions. The ARP is also loaded with the same value as ARB when an LST #1 instruction is
executed.
C
Carry Bit. C is set to 1 if the result of an addition generates a carry, or reset to 0 if the result of a subtraction generates a borrow.
Otherwise, C is reset after an addition or set after a subtraction, except if the instruction is ADD or SUB with a 16-bit shift. In
these cases, the ADD can only set and the SUB only reset the carry bit, but cannot affect it otherwise. The single-bit shift and
rotate instructions also affect C, as well as the SETC, CLRC, and LST #1 instructions. Branch instructions have been provided
to branch on the status of C. C is set to 1 on a reset.
CNF
On-chip RAM configuration-control bit. If CNF is set to 0, the reconfigurable data DARAM blocks are mapped to data space;
otherwise, they are mapped to program space. The CNF can be modified by the SETC CNF, CLRC CNF, and LST #1 instruc-
tions. RS sets the CNF to 0.
DP
Data memory page pointer. The 9-bit DP register is concatenated with the seven LSBs of an instruction word to form a direct
memory address of 16 bits. DP can be modified by the LST and LDP instructions.
INTM
Interrupt-mode bit. When INTM is set to 0, all unmasked interrupts are enabled. When set to 1, all maskable interrupts are
disabled. INTM is set and reset by the SETC INTM and CLRC INTM instructions. RS also sets INTM. INTM has no effect on
the unmaskable RS and NMI interrupts. Note that INTM is unaffected by the LST instruction. This bit is set to 1 by reset. It is
also set to 1 when a maskable interrupt trap is taken.
OV
Overflow-flag bit. As a latched overflow signal, OV is set to 1 when overflow occurs in the ALU. Once an overflow occurs, the
OV remains set until a reset, BCND/D on OV/NOV, or LST instructions clear OV.
OVM
Overflow-mode bit. When OVM is set to 0, overflowed results overflow normally in the accumulator. When set to 1, the
accumulator is set to either its most positive or negative value upon encountering an overflow. The SETC and CLRC
instructions set and reset this bit, respectively. LST can also be used to modify the OVM.
PM
Product-shift mode. If these two bits are 00, the multiplier’s 32-bit product is loaded into the ALU with no shift. If PM = 01, the
PREG output is left-shifted one place and loaded into the ALU, with the LSB zero-filled. If PM = 10, PREG output is left-shifted
by four bits and loaded into the ALU, with the LSBs zero-filled. PM = 11 produces a right shift of six bits, sign-extended. Note
that the PREG contents remain unchanged. The shift takes place when transferring the contents of the PREG to the ALU. PM
is loaded by the SPM and LST #1 instructions. PM is cleared by RS.
SXM
Sign-extension mode bit. SXM = 1 produces sign extension on data as it is passed into the accumulator through the scaling
shifter. SXM = 0 suppresses sign extension. SXM does not affect the definitions of certain instructions; for example, the ADDS
instruction suppresses sign extension regardless of SXM. SXM is set by the SETC SXM and reset by the CLRC SXM
instructions, and can be loaded by the LST #1. SXM is set to 1 by reset.
TC
Test/control flag bit. TC is affected by the BIT, BITT, CMPR, LST #1, and NORM instructions. TC is set to a 1 if a bit tested by
BIT or BITT is a 1, if a compare condition tested by CMPR exists between AR (ARP) and AR0, if the exclusive-OR function
of the two MSBs of the accumulator is true when tested by a NORM instruction. The conditional branch, call, and return
instructions can execute, based on the condition of TC.
XF
XF pin status bit. XF indicates the state of the XF pin, a general-purpose output pin. XF is set by the SETC XF and reset by
the CLRC XF instructions. XF is set to 1 by reset.
central processing unit
The TMS320F206 central processing unit (CPU) contains a 16-bit scaling shifter, a 16x16-bit parallel multiplier,
a 32-bit central arithmetic logic unit (CALU), a 32-bit accumulator, and additional shifters at the outputs of both
the accumulator and the multiplier. This section describes the CPU components and their functions. The
functional block diagram shows the components of the CPU.
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