參數(shù)資料
型號(hào)： TMS320F206PZL
元件分類： 數(shù)字信號(hào)處理
英文描述： 16-Bit Digital Signal Processor
中文描述： 16位數(shù)字信號(hào)處理器
文件頁數(shù)： 5/57頁
文件大?。?/td> 793K
代理商： TMS320F206PZL
TMS320F206
DIGITAL SIGNAL PROCESSOR
SPRS050A – NOVEMBER 1996 – REVISED APRIL 1998
5
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
TMS320F206 Terminal Functions (Continued)
TERMINAL
NAME
TYPE
DESCRIPTION
NO.
OSCILLATOR, PLL, AND TIMER SIGNALS (CONTINUED)
DIV1
DIV2
3
5
I
DIV1 and DIV2 provide clock-mode inputs.
DIV1–DIV2 should not be changed unless the RS signal is active.
PLL5V
10
I
The TMS320F206 is strictly a 5-V device. For this reason, the PLL5V pin should always be pulled high.
SERIAL PORT AND UART SIGNALS
CLKX
87
I/O/Z
Transmit clock. CLKX is a clock signal for clocking data from the serial-port transmit shift register (XSR) to the
DX data-transmit pin. The CLKX can be an input if the MCM bit in the synchronous serial-port control register
(SSPCR) is set to 0. CLKX can also be driven by the device at one-half of the CLKOUT1 frequency when
MCM = 1. If the serial port is not being used, CLKX goes into the high-impedance state when OFF is active
low. Value at reset is as an input.
CLKR
84
I/O/Z
Receive-clock input. External clock signal for clocking data from the DR (data-receive) pin into the serial-port
receive shift register (RSR). CLKR must be present during serial-port transfers. If the serial port is not being
used, CLKR can be sampled as an input by the IN0 bit of the SSPCR. This pin also functions as a frame-sync
output when the SSP is used in multichannel mode.
FSR
85
I/O/Z
Frame synchronization pulse for receive input. The falling edge of the FSR pulse initiates the data-receive
process, beginning the clocking of the RSR. FSR goes into the high-impedance state when OFF is active low.
This pin also functions as a frame-sync output when the SSP is used in multichannel mode.
FSX
89
I/O/Z
Frame synchronization pulse for transmit input/ouput. The falling edge of the FSX pulse initiates the
data-transmit process, beginning the clocking of the serial-port transmit shift register (XSR). Following reset,
FSX is an input. FSX can be selected by software to be an output when the TXM bit in the SSPCR is set
to 1. FSX goes into the high-impedance state when OFF is active low.
DR
86
I
Serial-data receive input. Serial data is received in the receive shift register (RSR) through the DR pin.
DX
90
O/Z
Serial-port transmit output. Serial data is transmitted from the transmit shift register (XSR) through the DX pin.
DX is in the high-impedance state when OFF is active low.
TX
93
O/Z
Asynchronous transmit data pin. TX is in the high-impedance state when OFF is active low.
RX
95
I
Asynchronous receive data pin
TEST SIGNALS
TRST
79
I
IEEE Standard 1149.1 (JTAG) test reset. TRST, when driven high, gives the scan system control of the
operations of the device. If TRST is driven low, the device operates in its functional mode, and the test signals
are ignored.
If the TRST pin is not driven, an external pulldown resistor must be used.
JTAG test clock. TCK is normally a free-running clock signal with a 50% duty cycle. The changes on the
test-access port (TAP) input signals (TMS and TDI) are clocked into the TAP controller, instruction register, or
selected test-data register on the rising edge of TCK. Changes at the TAP output signal (TDO) occur on the
falling edge of TCK.
TCK
78
I
TMS
81
I
JTAG test-mode select. TMS is clocked into the TAP controller on the rising edge of TCK.
TDI
80
I
JTAG test-data input. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK.
TDO
82
O/Z
JTAG test-data output. The contents of the selected register (instruction or data) are shifted out of TDO on the
falling edge of TCK. TDO is in the high-impedance state except when the scanning of data is in progress.
EMU0
76
I/O/Z
Emulator pin 0. When TRST is driven low, EMU0 must be high for activation of the OFF condition. When TRST
is driven high, EMU0 is used as an interrupt to or from the emulator system and is defined as an input/output
through the JTAG scan.
EMU1/OFF
77
I/O/Z
Emulator pin 1. Emulator pin 1 disables all outputs. When TRST is driven high, EMU1/OFF is used as an
interrupt to or from the emulator system and is defined as an input/output through the JTAG scan. When TRST
is driven low, this pin is configured as OFF. EMU1/OFF, when active low, puts all output drivers in the
high-impedance state. Note that OFF is used exclusively for testing and emulation purposes (not for
multiprocessing applications). Therefore, for the OFF condition, the following apply:
TRST = 0
EMU0 = 1
EMU1/OFF = 0
I = input, O = output, Z = high impedance, PWR = power, GND = ground
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