參數(shù)資料
型號： TMS320F206PZL
元件分類： 數(shù)字信號處理
英文描述： 16-Bit Digital Signal Processor
中文描述： 16位數(shù)字信號處理器
文件頁數(shù)： 15/57頁
文件大小： 793K
代理商： TMS320F206PZL
TMS320F206
DIGITAL SIGNAL PROCESSOR
SPRS050A – NOVEMBER 1996 – REVISED APRIL 1998
15
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
auxiliary registers and auxiliary-register arithmetic unit (ARAU)
The ’F206 provides a register file containing eight auxiliary registers (AR0–AR7). The auxiliary registers are
used for indirect addressing of the data memory or for temporary data storage. For indirect data memory
addressing, the address of the desired memory location is placed into the selected auxiliary register. These
registers are referenced with a 3-bit auxiliary register pointer (ARP) that is loaded with a value from 0 through 7,
designating AR0 through AR7, respectively. The auxiliary registers and the ARP can be loaded from data
memory, the ACC, the product register, or by an immediate operand defined in the instruction. The contents of
these registers can also be stored in data memory or used as inputs to the CALU.
The auxiliary register file (AR0–AR7) is connected to the auxiliary register arithmetic unit (ARAU). The ARAU
can autoindex the current auxiliary register while the data memory location is being addressed. Indexing either
by
±
1 or by the contents of the AR0 register can be performed. As a result, accessing tables of information does
not require the CALU for address manipulation; therefore, the CALU is free for other operations in parallel.
memory
The ’F206 implements three separate address spaces for program memory, data memory, and I/O. Each space
accommodates a total of 64K 16-bit words. Within the 64K words of data space, the 256 to 32K words at the
top of the address range can be defined to be external global memory in increments of powers of two, as
specified by the contents of the global memory allocation register (GREG). Access to global memory is
arbitrated using the global memory bus request (BR) signal.
On the ’F206, the first 96 (0–5Fh) data memory locations are allocated for memory-mapped registers or
reserved. This memory-mapped register space contains various control and status registers including those for
the CPU.
The TMS320F206 device includes 544 x 16 words of dual-access RAM (DARAM), 4K x 16 single-access RAM
(SARAM), and 32K x 16 program flash memory. Table 7 shows the mapping of these memory blocks and the
appropriate control bits and pins. Figure 1 shows the effects of the memory control pin MP/MC and the control
bit CNF on the mapping of the respective memory spaces to on-chip or off-chip. The PON and DON bits select
the SARAM (4K) mapping in program, data, or both. See Table 8 for details of the PMST register, and PON and
DON bits. At reset, these bits are 11, which selects the SARAM in program and data space. The SARAM
addresses are 0x800h in data and 0x8000h in program memory.
At reset, if the MP/MC pin is held high, the device is in microprocessor mode and the program address branches
to 0x0000h (external program space). The MP/MC pin status is latched in the PMST register (bit 0). As long as
this bit remains high, the device is in microprocessor mode. PMST register bits can be read and modified in
software. If bit 0 is cleared to 0, the device enters microcontroller mode and transfers control to the on-chip flash
memory at 0x0000.
The on-chip data memory blocks B0 and B1 are 256
address ranges within the ’F206 memory map. For example, when CNF = 0, B0 is mapped in data space at
addresses 0100–01FFh, and also at addresses 0200–02FFh. Corresponding addresses of the two ranges
(0100h and 0200h, 0101h and 0201h, ...) access the same memory locations within B0. Similarly, when
CNF = 1, B0 is mapped in program space at addresses 0FE00–0FEFFh, and also at addresses
0FF00–0FFFFh. The B1 block is always mapped in data space at addresses 0300–03FFh, and also at
0400–04FFh.
16 words each, and these blocks are mapped to dual
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