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參數(shù)資料
| 型號： | TMS320F206PZL |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 16-Bit Digital Signal Processor |
| 中文描述： | 16位數(shù)字信號處理器 |
| 文件頁數(shù)： | 14/57頁 |
| 文件大?。?/td> | 793K |
| 代理商： | TMS320F206PZL |
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TMS320F206
DIGITAL SIGNAL PROCESSOR
SPRS050A – NOVEMBER 1996 – REVISED APRIL 1998
14
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
central arithmetic logic unit (continued)
The CALU overflow saturation mode can be enabled/disabled by setting/resetting the OVM bit of ST0. Setting
the OVM status register bit selects the overflow saturation mode. When the CALU is in the overflow saturation
mode and an overflow occurs, the overflow flag is set and the accumulator is loaded with either the most positive
or the most negative value representable in the accumulator, depending upon the direction of the overflow. The
value of the accumulator upon saturation is 07FFFFFFFh (positive) or 080000000h (negative). If the OVM
(overflow mode) status register bit is reset and an overflow occurs, the overflowed results are loaded into the
accumulator without modification. (Note that logical operations cannot result in overflow.)
The CALU can execute a variety of branch instructions that depend on the status of the CALU and accumulator.
These instructions can be executed conditionally, based on various combinations of the associated status bits.
For overflow management, these conditions include the OV (branch on overflow) and EQ (branch on
accumulator equal to zero). In addition, the BACC (branch-to-address in accumulator) instruction provides the
ability to branch to an address specified by the accumulator (computed goto). Bit test instructions (BIT and
BITT), which do not affect the accumulator, allow the testing of a specified bit of a word in data memory.
The CALU also has a carry bit (bit 9 of status register ST1) that facilitates efficient computation of
extended-precision products and additions or subtractions. The carry bit is also useful in overflow management.
The carry bit is affected by the following operations:
Additions to and subtractions from the accumulator:
C = 0: When the result of a subtraction generates a borrow.
When the result of an addition does not generate a carry. (Exception: When the ADD instruction is
used with a shift of 16 and no carry is generated, the ADD instruction has no effect on C.)
C = 1: When the result of an addition generates a carry.
When the result of a subtraction does not generate a borrow. (Exception: When the SUB instruction
is used with a shift of 16 and no borrow is generated, the SUB instruction has no effect on C.)
Single-bit shifts and rotations of the accumulator value. During a left shift or rotation, the most significant
bit of the accumulator is passed to C; during a right shift or rotation, the least significant bit is passed to C.
Note: the carry bit is set to “1” on a hardware reset.
The ADDC (add to accumulator with carry) and SUBB (subtract from accumulator with borrow) instructions
provided, use the previous value of carry in their addition/subtraction operation.
accumulator
The 32-bit accumulator is the registered output of the CALU. It can be split into two 16-bit segments for storage
in data memory. Shifters at the output of the accumulator provide a left shift of 0 to 7 places. This shift is
performed while the data is being transferred to the data bus for storage. The contents of the accumulator
remain unchanged. When the post-scaling shifter is used on the high word of the accumulator (bits 16–31), the
MSBs are lost and the LSBs are filled with bits shifted in from the low word (bits 0–15). When the post-scaling
shifter is used on the low word, the LSBs are zero-filled.
The SFL and SFR (in-place one-bit shift to the left/right) instructions and the ROL and ROR (rotate to the
left/right) instructions implement shifting or rotating of the accumulator contents through the carry bit. The SXM
bit affects the definition of the SFR (shift accumulator right) instruction. When SXM=1, SFR performs an
arithmetic right shift, maintaining the sign of the accumulator data. When SXM=0, SFR performs a logical shift,
shifting out the LSBs and shifting in a zero for the MSB. The SFL (shift accumulator left) instruction is not affected
by the SXM bit and behaves the same in both cases, shifting out the MSB and shifting in a zero. Repeat (RPT)
instructions can be used with the shift and rotate instructions for multiple-bit shifts.
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| TMS320F241FN | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 16B 5V fixed point DSP w/ Flash RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
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