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參數(shù)資料
| 型號(hào)： | TMXF84622 |
| 英文描述： | TMXF84622 155 Mbits/s/622 Mbits/s Interface SONET/SDH x84/x63 Ultramapper |
| 中文描述： | TMXF84622 155 Mbits/s/622 Mbits /秒接口的SONET / SDH x84/x63 Ultramapper |
| 文件頁數(shù)： | 33/62頁 |
| 文件大?。?/td> | 902K |
| 代理商： | TMXF84622 |
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Agere Systems Inc.
33
Advance Data Sheet, Rev. 2
July 2001
SONET/SDH x84/x63 Ultramapper
TMXF84622 155 Mbits/s/622 Mbits/s Interface
3 Pin Information
(continued)
Table 1. Pin Descriptions
(continued)
* O
1
indicates external pull-up recommended (unused or system required),
I/O
2
indicates external pull-down recommended (unused or system required),
I
D
; I/O
D
indicate internal pull-down,
I
U
indicates internal pull-up.
Transmit path convention is toward the high-speed fiber output. Note that LINERX signals are labeled Receive, as seen from the cross con-
nect perspective.
Pin
Symbol
Type I/O*
Multifunction System Interface
Description
Note:
Pin functional descriptions are representative configurations. Configuration is limited by the I/O definition
and the flexibility of the internal cross-connect.
LINE Transmit Path Direction (60)
A3, F8, B5, A4,
B6, B7, E9,
F10, B8, A7,
B9, E11, B10,
E12, A10, F13,
A11, F14, E14,
C14, F15, E15,
C15, B15, F17,
A16, C17, B18,
E18, B19
VT Mapper: Receive DS1/E1/VC data input.
LINERXDATA[30:1]
—
I
D
Configurable Inputs to the Internal Cross Connect.
Transport Modes:
Framer
—
LIU: Received positive-rail or single-rail DS1/E1
line data input (sourced from an external LIU).
M12 or E12: Normally used as receive DS1/E1 data input. If
DS1/E1
’
s come from internal source, these pins may also be
used as DS2/E2 inputs.
M23 or E23: Receive DS2/E2 data input. Up to 21 DS2/12
E2 signals may be assigned to any of the 30 LINERXDATA
inputs.
I/O
D
Configurable Inputs to the Internal Cross Connect.
Transport Modes:
Framer
—
LIU: Receive DS1/E1 line clock input
E6, B4, C5, C6,
E8, A5, F9, A6,
C8, F11, C9,
A8, F12, A9,
C11, B11, C12,
B12, A12, B13,
A13, B14, A14,
F16, A15, B16,
E17, B17, C18,
A19
LINERXCLK[30:1]
—
M12 or E12: Normally used as receive DS1/E1 line clock
input (unless for demand clocking mode in which they are
used as clock outputs). If DS1/E1 signals come from internal
source, these pins may carry DS2/E2 clk input.
VT Mapper: Receive DS1/E1/VC line clock input
M23 or E23: Receive DS2/E2 clock input/output. Up to
21 DS2/12 E2 signals may be assigned to any of the 30 LIN-
ERXCLK inputs.
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