參數(shù)資料
型號: TMXF84622
英文描述: TMXF84622 155 Mbits/s/622 Mbits/s Interface SONET/SDH x84/x63 Ultramapper
中文描述: TMXF84622 155 Mbits/s/622 Mbits /秒接口的SONET / SDH x84/x63 Ultramapper
文件頁數(shù): 38/62頁
文件大?。?/td> 902K
代理商: TMXF84622
38
Agere Systems Inc.
Advance Data Sheet, Rev. 2
July 2001
SONET/SDH x84/x63 Ultramapper
TMXF84622 155 Mbits/s/622 Mbits/s Interface
3 Pin Information
(continued)
Table 1. Pin Descriptions
(continued)
* O
1
indicates external pull-up recommended (unused or system required),
I/O
2
indicates external pull-down recommended (unused or system required),
I
D
; I/O
D
indicate internal pull-down,
I
U
indicates internal pull-up.
Pin
Symbol
Type
I/O
*
Description
M13/E13 Mux/DeMUX Block
Receive (DeMUX) Direction (6)
I
D
E1 X Clock.
This clock signal is used to generate E1 AIS
(all 1s). It must be 2.048 MHz ± 50 ppm, or x16, x32 of
2.048 MHz.
I
D
DS1 X Clock
. This clock signal is used to generate DS1
AIS (all 1s). It must be 1.544 MHz ± 32 ppm, or x16, x32 of
1.544 MHz.
I
D
DS2 AIS Clock.
A 6.312 MHz ± 30 ppm clock input used as
DS2 AIS clock or DS2 data output clock.
VC11 AIS Clock
. A 1.664 MHz input. In the VTMPR mode,
this clock is used to generate VC11 AIS.
I
D
E2 AIS Clock.
A 8.448 MHz ± 30 ppm clock input used as
E2 AIS clock or E2 data output clock.
VC12 AIS Clock
. A 2.224 MHz input. In the VTMPR mode,
this clock is used to generate VC12 AIS.
I
D
DS3 X Clock.
A 44.736 MHz ± 20 ppm clock input for DS3
DJA.
I
D
E3 X Clock.
A 34.768 MHz ± 20 ppm clock input for E3
DJA.
VT Mapper Block
Transmit Direction (3)
I
D
Low-Order Path Overhead Clock.
I
D
Low-Order Path Overhead Data (O-Bits, V5, J2, Z6/N2,
Z7, and K4 Byte).
I
D
Valid LOPOHDATAIN.
Receive Direction (3)
O
Low-Order Path Overhead Clock.
O
Low-Order Path Overhead Data (Line and Path REI and
RDI, O-Bits, V5, J2, Z6/N2, and Z7/K4 Byte).
O
Valid LOPOHDATAOut.
AP21
E1XCLK
AK20
DS1XCLK
R1
DS2AISCLK
U6
E2AISCLK
A21
DS3XCLK
F18
E3XCLK
B22
C21
LOPOHCLKIN
LOPOHDATAIN
A22
LOPOHVALIDIN
F20
B21
LOPOHCLKOUT
LOPOHDATAOUT
E20
LOPOHVALIDOUT
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