TPS2345
SLUS503B – MARCH 2002 – REVISED AUGUST 2002
6
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pin descriptions
AGND: Analog ground reference for the device.
BD_SEL#: Logic low enable input for back-end power. In the CompactPCIR application, this pin ties to the
short–pin BD_SEL# input to the plug-in slot. When the input supplies are above the device minimums, and this
pin is asserted low the TPS2345 begins the sequential ramp–up of the back-end supplies. Pulling this input high
(>2 V) turns off power to the back-end planes, and puts the TPS2345 into low-power sleep mode.
CPGND: Charge pump ground pin for the device.
CPUMP: Charge pump resevoir capacitor connection. An external capacitor of value 0.1
F to 1 F must be
connected between this pin and CPGND. The capacitor provides charge storage for the internal charge pump
for gate drive of the four external N-channel FETs.
CS1, CS2, CS3: These pins tie to the load side of the Channel 1, 2, and 3 current sense resistors, respectively.
They are used in conjunction with the VIN1, VIN2 and VIN3 inputs to provide load current magnitude information
to each of the positive rail LCAs.
CS4: This pin ties to the more positive side of the Channel 4 current sense resistor (common with the pass FET
source). It is used in conjunction with the VIN4 input to provide Channel 4 current magnitude information to the
negative rail LCA.
GATE1, GATE2, GATE3, GATE4: Gate drive outputs for the Channel 1 through Channel 4 pass FETs,
respectively. The gates are driven according to the supply voltage, enable, sequence programming and load
current conditions of the add-in board.
HEALTHY#: Open-drain output asserted low to signal a back-end power good condition. In the CompactPCIR
application, this signal is an indication of the board’s suitablility to be connected to the CompactPCIR bus. The
output is false when back-end power is not enabled, if any of the back-end voltage is not within the
factory-programmed tolerances of the undervoltage and overvoltage comparators, or as a result of an
overcurrent indication on any supply controller, or a fault time-out on any supply during linear ramp-up.
IRAMP: Current ramp programming pin. A capacitor connected between this pin and ground determines the
maximum slew rate of the load current during ramp-up and ramp-down of the three positive back-end voltages.
This same capacitor is also used to establish the time limit for ramping each of the supply outputs.
PRECHG: Bias supply of 1 V for bus signal precharge. During plug-in insertion events, this output provides bias
supply to precharge the bus signal lines according to the requirements of the CompactPCIR Hot Swap
specification.
RGND: Reference ground input for the device.
VIN1: Channel 1 supply (12-V) input voltage sense. This pin is connected to the 12-V power supply input to
the add-in card. The supply potential is tested against the undervoltage limits prior to ramping voltage to the
back-end 12-V plane. The input supply also serves as the reference potential for the internally generated current
limit (IMAX) reference of the Channel 1 LCA. This pin also serves as the VCC supply for the TPS2345.
VIN2: Channel 2 supply (5-V) input voltage sense. This pin is connected to the 5-V power supply input to the
add-in card. The supply potential is tested against the undervoltage limits prior to ramping voltage to the
back-end 5-V plane. The input supply also serves as the reference potential for the internally generated current
limit (IMAX) reference of the Channel 2 LCA. This pin also serves as the supply input for the precharge bias
output.
VIN3: Channel 3 supply (3.3-V) input voltage sense. This pin is connected to the 3.3-V power supply input to
the add-in card. The supply potential is tested against the undervoltage limits prior to ramping voltage to the
back-end 3.3-V plane. The input supply also serves as the reference potential for the internally generated
current limit (IMAX) reference of the Channel 3 LCA.