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參數(shù)資料
| 型號： | TPS2345PWNRND |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 電源管理 |
| 英文描述： | 4-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO24 |
| 封裝： | GREEN, TSSOP-24 |
| 文件頁數(shù)： | 32/32頁 |
| 文件大?。?/td> | 621K |
| 代理商： | TPS2345PWNRND |
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TPS2345
SLUS503B – MARCH 2002 – REVISED AUGUST 2002
9
www.ti.com
detailed description
The primary circuit blocks of the TPS2345 include internal supply generation, a charge pump, a state machine,
programmable ramp generator, precharge circuitry, and a ROM data cell. In addition, each of the four channels
contains a gate control block which includes the linear control amplifier (LCA), programmable current source,
and the voltage sense circuitry (see Figure 1). The gate drive blocks are virtually identical, except that the
Channel 4 block, controlling the negative voltage channel, adds some scaling and level shift circuitry to adjust
the polarity of the sense signals to that of the internal circuitry.
+
1V
+
2.5V
SUPPLY
SECTION
CHARGE
PUMP
CPOK
UVLO
VIN1
UVOV1
LEVEL[15:0]
IRAMP
VIN2
STATE
MACHINE
UVOV[4:1]
100
S
ROM
DATA
PRE–
CHARGE
+
VIMAX3
LCA/
V–SNS3
VIMAX4
LS
+
LCA/
V–SNS4
VIMAX2
+
LCA/
V–SNS2
VIMAX1
+
LCA/
V–SNS1
EN1
EN2
EN3
EN4
/FLT
OC[4:1]
UVLO
CPOK
EN
ORD[8:0]
FS
VS1
OC1
UVOV3
OC3
UVOV2
OC2
UVOV4
OC4
VIN2
VA
EN1
EN2
EN3
EN4
BD_SEL#
HEALTHY#
VIN1
VIN3
VIN4
3
12
11
14
8
16
13
15
5
22
23
24
21
20
2
4
1
6
17
10
VS2
VS4
VS3
GATE1
CS1
CS2
CS4
CS3
GATE2
GATE4
GATE3
19
7
18
/CHG
RGND
AGND
PRECHG
CPGND
CPUMP
+
DAC
RAMP
GENERATOR
3
UP
CH_SEL[4:1]
9
MUX
Figure 1. TPS2345 block diagram
The supply generation block contains voltage regulators and references to generate the various bias voltages
used internally by the TPS2345. An undervoltage lockout (UVLO) function is used to ensure proper device
turn-on once the VIN1 input has attained the UVLO threshold of about 2.5 V. In addition, an on-chip charge pump
steps up the VIN1 input to generate the high voltage used by the LCAs to drive the pass MOSFET gates. Burst
regulation of the charge pump limits the output to about 20.5 V (peak), with about a 1-V hysteresis. During
steady-state load operation, sufficient gate overdrive is ensured to fully enhance the external MOSFETs, while
not exceeding the typical 20-V VGS rating of common N-channel MOSFETs, even on the low-voltage channels.
The state machine block contains the logic to control the ramp-up and ramp-down sequencing, ramp generator
operation, and fault management. It uses voltage and current monitor outputs, along with the device enable
status and programmed order information to determine which channel is to be acted on, whether ramp-up,
ramp-down or steady-state operation is required, and the present healthy or faulted states of the back-end
supplies. A nominal 100–
S digital filter is applied to the BD_SEL# input to help protect against false triggering
in systems not implementing hardware connection control. The filter acts on both high-to-low and low-to-high
transitions of the enable input.
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