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參數(shù)資料
| 型號： | TPS65023QRHARQ1 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 電源管理 |
| 英文描述： | POWER SUPPLY SUPPORT CKT, PQCC40 |
| 封裝： | 6 X 6 MM, GREEN, PLASTIC, MO-220VJJD-2, VQFN-40 |
| 文件頁數(shù)： | 16/54頁 |
| 文件大?。?/td> | 1546K |
| 代理商： | TPS65023QRHARQ1 |
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I
=
PFMDCDC1 enter
I
=
PFMDCDC2 enter
I
=
PFMDCDC3 enter
VINDCDC1
VINDCDC2
VINDCDC3
24 W
26 W
39 W
I
=
PFMDCDC1 leave
I
=
PFMDCDC2 leave
I
=
PFMDCDC3 leave
VINDCDC1
VINDCDC2
VINDCDC3
18 W
20 W
29 W
www.ti.com
SLVS927C – MARCH 2009 – REVISED MAY 2010
During PWM operation, the converters use a unique fast response voltage mode controller scheme with input
voltage feed-forward to achieve good line and load regulation allowing the use of small ceramic input and output
capacitors. At the beginning of each clock cycle initiated by the clock signal, the P-channel MOSFET switch is
turned on. The inductor current ramps up until the comparator trips and the control logic turns off the switch. The
current limit comparator also turns off the switch if the current limit of the P-channel switch is exceeded. After the
adaptive dead time used to prevent shoot through current, the N-channel MOSFET rectifier is turned on, and the
inductor current ramps down. The next cycle is initiated by the clock signal, again turning off the N-channel
rectifier and turning on the P-channel switch.
The three dc-dc converters operate synchronized to each other with the VDCDC1 converter as the master. A
180° phase shift between the VDCDC1 switch turn on and the VDCDC2 and a further 90° shift to the VDCDC3
switch turn on decreases the input RMS current and smaller input capacitors can be used. This is optimized for a
typical application where the VDCDC1 converter regulates a Li-Ion battery voltage of 3.7 V to 1.2 V, the
VDCDC2 converter from 3.7 V to 1.8 V, and the VDCDC3 converter from 3.7 V to 3.3 V. The phase of the three
converters can be changed using the CON_CTRL register.
Power-Save Mode Operation (PSM)
As the load current decreases, the converters enter the power-save mode operation. During PSM, the converters
operate in a burst mode (PFM mode) with a frequency between 750 kHz and 2.25 MHz, nominal for one burst
cycle. However, the frequency between different burst cycles depends on the actual load current and is typically
far less than the switching frequency with a minimum quiescent current to maintain high efficiency.
In order to optimize the converter efficiency at light load, the average current is monitored and if in PWM mode
the inductor current remains below a certain threshold, then PSM is entered. The typical threshold to enter PSM
is calculated as follows:
(1)
During the PSM the output voltage is monitored with a comparator, and by maximum skip burst width. As the
output voltage falls below the threshold, set to the nominal VO, the P-channel switch turns on and the converter
effectively delivers a constant current defined as follows.
(2)
If the load is below the delivered current then the output voltage rises until the same threshold is crossed in the
other direction. All switching activity ceases, reducing the quiescent current to a minimum until the output voltage
has again dropped below the threshold. The power save mode is exited, and the converter returns to PWM mode
if either of the following conditions are met:
1. the output voltage drops 2% below the nominal VO due to increasing load current
2. the PFM burst time exceeds 16 × 1/fs (7.11 ms typical).
These control methods reduce the quiescent current to typically 14 mA per converter, and the switching activity to
Copyright 2009–2010, Texas Instruments Incorporated
23
Product Folder Link(s): TPS65023-Q1
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