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參數(shù)資料
| 型號： | TPS65023QRHARQ1 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 電源管理 |
| 英文描述： | POWER SUPPLY SUPPORT CKT, PQCC40 |
| 封裝： | 6 X 6 MM, GREEN, PLASTIC, MO-220VJJD-2, VQFN-40 |
| 文件頁數(shù)： | 19/54頁 |
| 文件大?。?/td> | 1546K |
| 代理商： | TPS65023QRHARQ1 |
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SLVS927C – MARCH 2009 – REVISED MAY 2010
www.ti.com
System Reset and Control Signals
The RESPWRON signal can be used as a global reset for the application. It is an open drain output. The
RESPWRON signal is generated according to the power good comparator of VRTC, and remains low for tnrespwron
seconds after VRTC has risen above 2.52 V (falling threshold is 2.4 V, 5% hysteresis). tnrespwron is set by an
external capacitor at the TRESPWRON pin. 1 nF gives typically 100 ms. RESPWRON is also triggered by the
HOT_RESET input. This input is internally debounced, with a filter time of typically 30 ms.
The PWRFAIL and LOW_BAT signals are generated by two voltage detectors using the PWRFAIL_SNS and
LOWBAT_SNS input signals. Each input signal is compared to a 1 V threshold (falling edge) with 5% (50 mV)
hysteresis.
The DCDC1 converter is reset to its default output voltage defined by the DEFDCDC1 input, when HOT_RESET
is asserted. Other I2C registers are not affected. Generally, the DCDC1 converter is set to its default voltage with
one of these conditions: HOT_RESET active, VRTC lower than its threshold voltage, undervoltage lockout
(UVLO) condition, or RESPWRON active.
DEFLDO1 and DEFLDO2
These two pins are used to set the default output voltage of the two 200 mA LDOs. The digital value applied to
the pins is latched during power up and determines the initial output voltage according to Table 3. The voltage of
both LDOs can be changed during operation with the I2C interface as described in the interface description.
Table 3.
DEFLDO2
DEFLDO1
VLDO1
VLDO2
0
1.3 V
3.3 V
0
1
2.8 V
3.3 V
1
0
1.3 V
1.8 V
1
1.8 V
3.3 V
Interrupt Management and the INT Pin
The INT pin combines the outputs of the PGOOD comparators from each dc-dc converter and the LDOs. The
INT pin is used as a POWER_OK pin to indicate when all enabled supplies are in regulation. The INT pin
remains active (low state) during power up as long as all enabled power rails are below their regulation limit.
Once the last enabled power rail is within regulation, the INT pin transitions to a high state.
During operation, if one of the enabled supplies goes out of regulation, INT transitions to a low state, and the
corresponding bit in the PGOODZ register goes high. If the supply goes back to its regulation limits, INT
transitions back to a high state.
While INT is in an active low state, reading the PGOODZ register via the I2C bus forces INT into a high-Z state.
Since this pin requires an external pullup resistor, the INT pin transitions to a logic high state even though the
supply in question is still out of regulation. The corresponding bit in the PGOODZ register still indicates that the
power rail is out of regulation.
Interrupts can be masked using the MASK register. The default operation is to not mask any DCDC or LDO
interrupts, because these provide the POWER_OK function.
26
Copyright 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS65023-Q1
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| TPS65023QRSBRQ1 | 功能描述:電池管理 Auto Cat 6Ch Pwr Mgmt IC RoHS:否 制造商:Texas Instruments 電池類型:Li-Ion 輸出電壓:5 V 輸出電流:4.5 A 工作電源電壓:3.9 V to 17 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:VQFN-24 封裝:Reel |
| TPS65023RSBG4 | 制造商:Texas Instruments 功能描述: |
| TPS65023RSBR | 功能描述:電池管理 6Ch Pwr Mgmt IC RoHS:否 制造商:Texas Instruments 電池類型:Li-Ion 輸出電壓:5 V 輸出電流:4.5 A 工作電源電壓:3.9 V to 17 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:VQFN-24 封裝:Reel |
| TPS65023RSBRG4 | 功能描述:電池管理 6Ch Pwr Mgmt IC RoHS:否 制造商:Texas Instruments 電池類型:Li-Ion 輸出電壓:5 V 輸出電流:4.5 A 工作電源電壓:3.9 V to 17 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:VQFN-24 封裝:Reel |
| TPS65023RSBT | 功能描述:電池管理 6-Channel Power Management IC RoHS:否 制造商:Texas Instruments 電池類型:Li-Ion 輸出電壓:5 V 輸出電流:4.5 A 工作電源電壓:3.9 V to 17 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:VQFN-24 封裝:Reel |
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