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SLVS927C – MARCH 2009 – REVISED MAY 2010
Low-Dropout Voltage Regulators
The low dropout voltage regulators are designed to operate well with low value ceramic input and output
capacitors. They operate with input voltages down to 1.5 V. The LDOs offer a maximum dropout voltage of
300 mV at rated output current. Each LDO supports a current limit feature. Both LDOs are enabled by the
LDO_EN pin, both LDOs can be disabled or programmed via the serial interface using the REG_CTRL and
LDO_CTRL registers. The LDOs also have reverse conduction prevention. This allows the possibility to connect
external regulators in parallel in systems with a backup battery. The TPS65023 step-down and LDO voltage
regulators automatically power down when the VCC voltage drops below the UVLO threshold or when the junction
temperature rises above 160°C.
Power Good Monitoring
Both the LDO1 and LDO2 linear regulators have power good comparators. Each comparator indicates when the
relevant output voltage has dropped 10% below its target value, with 5% hysteresis. The outputs of these
comparators are available in the PGOODZ register via the serial interface. An interrupt is generated when any
voltage rail drops below the 10% threshold. The comparators are disabled when the LDOs are disabled and the
relevant PGOODZ register bits indicate that power is good.
Undervoltage Lockout
The undervoltage lockout circuit for the five regulators on the TPS65023 prevents the device from malfunctioning
at low-input voltages and from excessive discharge of the battery. It disables the converters and LDOs. The
UVLO circuit monitors the VCC pin, the threshold is set internally to 2.35 V with 5% (120 mV) hysteresis. Note
that when any of the dc-dc converters are running, there is an input current at the VCC pin, which is up to 3 mA
when all three converters are running in PWM mode. This current needs to be taken into consideration if an
external RC filter is used at the VCC pin to remove switching noise from the TPS65023 internal analog circuitry
supply.
Power-Up Sequencing
The TPS65023 power-up sequencing is designed to be entirely flexible and customer driven. This is achieved by
providing separate enable pins for each switch-mode converter, and a common enable signal for the LDOs. The
relevant control pins are described in
Table 2.Table 2. Control Pins and Status Outputs for DC-DC Converters
PIN NAME
I/O
FUNCTION
Defines the default voltage of the VDCDC3 switching converter. DEFDCDC3 = 0 defaults VDCDC3 to
DEFDCDC3
I
1.8 V, DEFDCDC3 = VCC defaults VDCDC3 to 3.3 V.
Defines the default voltage of the VDCDC2 switching converter. DEFDCDC2 = 0 defaults VDCDC2 to
DEFDCDC2
I
1.8 V, DEFDCDC2 = VCC defaults VDCDC2 to 3.3 V.
Defines the default voltage of the VDCDC1 switching converter. DEFDCDC1 = 0 defaults VDCDC1 to 1.2
DEFDCDC1
I
V, DEFDCDC1 = VCC defaults VDCDC1 to 1.6 V.
DCDC3_EN
I
Set DCDC3_EN = 0 to disable and DCDC3_EN = 1 to enable the VDCDC3 converter
DCDC2_EN
I
Set DCDC2_EN = 0 to disable and DCDC2_EN = 1 to enable the VDCDC2 converter
DCDC1_EN
I
Set DCDC1_EN = 0 to disable and DCDC1_EN = 1 to enable the VDCDC1 converter
The HOT_RESET pin generates a reset (RESPWRON) for the processor.HOT_RESET does not alter any
TPS65023 settings except the output voltage of VDCDC1. Activating HOT_RESET sets the voltage of
HOT_RESET
I
VDCDC1 to its default value defined with the DEFDCDC1 pin. HOT_RESET is internally de-bounced by the
TPS65023.
RESPWRON is held low when power is initially applied to the TPS65023. The VRTC voltage is monitored:
RESPWRON
O
RESWPRON is low when VRTC < 2.4 V and remains low for a time defined by the external capacitor at the
TRESPWRON pin. RESPWRON can also be forced low by activation of the HOT_RESET pin.
TRESPWRON
I
Connect a capacitor here to define the RESET time at the RESPWRON pin (1 nF typically gives 100 ms).
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