參數(shù)資料
型號(hào): TPS65023QRHARQ1
廠商: TEXAS INSTRUMENTS INC
元件分類(lèi): 電源管理
英文描述: POWER SUPPLY SUPPORT CKT, PQCC40
封裝: 6 X 6 MM, GREEN, PLASTIC, MO-220VJJD-2, VQFN-40
文件頁(yè)數(shù): 22/54頁(yè)
文件大小: 1546K
代理商: TPS65023QRHARQ1
DataLine
Stable;
DataValid
DATA
CLK
Change
ofData
Allowed
DATA
CLK
CE
S
P
STARTCondition
STOP Condition
SCLK
SDAT
Start
Slave Address
Register Address
Data
0
A6
A5
A4
A0
R/W
R7
R6
R5
R0
D7
D6
D5
D0
ACK
0
Stop
Note:SLAVE=TPS65020
www.ti.com
SLVS927C – MARCH 2009 – REVISED MAY 2010
For normal data transfer, DATA is allowed to change only when CLK is low. Changes when CLK is high are
reserved for indicating the start and stop conditions. During data transfer, the data line must remain stable
whenever the clock line is high. There is one clock pulse per bit of data. Each data transfer is initiated with a start
condition and terminated with a stop condition. When addressed, the TPS65023 device generates an
acknowledge bit after the reception of each byte. The master device (microprocessor) must generate an extra
clock pulse that is associated with the acknowledge bit. The TPS65023 device must pull down the DATA line
during the acknowledge clock pulse so that the DATA line is a stable low during the high period of the
acknowledge clock pulse. The DATA line is a stable low during the high period of the acknowledge–related clock
pulse. Setup and hold times must be taken into account. During read operations, a master must signal the end of
data to the slave by not generating an acknowledge bit on the last byte that was clocked out of the slave. In this
case, the slave TPS65023 device must leave the data line high to enable the master to generate the stop
condition
Figure 30. Bit Transfer on the Serial Interface
Figure 31. Start and Stop Conditions
Figure 32. Serial Interface Write to TPS65023 Device
Copyright 2009–2010, Texas Instruments Incorporated
29
Product Folder Link(s): TPS65023-Q1
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