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| 型號： | TPS65040ZQER |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 電源管理 |
| 英文描述： | 8-CHANNEL POWER SUPPLY MANAGEMENT CKT, PBGA71 |
| 封裝： | 5 X 5 MM, 0.50 MM PITCH, GREEN, PLASTIC, MICRO, BGA-71 |
| 文件頁數(shù)： | 10/73頁 |
| 文件大?。?/td> | 1928K |
| 代理商： | TPS65040ZQER |
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ELECTRICAL CHARACTERISTICS (continued)
SLVS708B – NOVEMBER 2006 – REVISED APRIL 2007
Over recommended input conditions, T
A = –30°C to 85°C, typical values are VBAT = 3.8 V, VIO1V8 = 1.85 V at TA = 25°C
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AFCDAC (D/A CONVERTER)
Resolution
12
bit
Differential non-linearity
DNL
–1
1
LSB
error(1)
Monotony increase
Specified
Full scale code digital input
2.4
2.45
2.5
V
VO(AFC)
Output voltage
Zero scale code digital input
0.2
0.25
0.3
V
Input code = 80h
1.3
1.35
1.4
V
ISD(AFC)
Shutdown current(2)
VBN1 pin at TA = 25°C
1
A
IQ(AFC)
Quiescent current(3)
VBN1 pin, ILOAD = 0 mA at TA = 25°C, Default code set
220
260
A
r[PSCNTAFC] (4) = 1 and SYSCLK_EN pin = VVIO, Zero
Settling time1(1)
scale code to full scale code (95%) or full scale code to zero
100
s
scale code (95%) RL = 100 k, RS = 1 k, C = 0.01 F
tSET(AFC)
r[PSCNTAFC] = 1 and SYSCLK_EN pin = VVIO, Zero scale
Settling time2(1)
code to full scale code (95%) or full scale code to zero scale
3.0
ms
code (95%) RL = 100 k, RS = 10 k, C= 0.1 F
r[PSCNTAFC] = 1 and SYSCLK_EN pin = 0V to VVIO, or
SYSCLK_EN pin = VVIO and r[PSCNTAFC] = 0 to 1(1),
Startup time1
600
s
Default scale code (95%) RL = 100 k, RS = 1 k, C = 0.01
F
tST(AFC)
r[PSCNTAFC] = 1 and SYSCLK_EN pin = 0V to VVIO, or
SYSCLK_EN pin = VVIO and r[PSCNTAFC] = 0 to 1(1),
Startup time2
3.5
ms
Default scale code (95%) RL = 100 k, RS = 10 k, C = 0.1
F
RO(AFC)
Output impedance
r[PSCNTAFC] = 1 and SYSCLK_EN pin =VVIO
20
RL
Resistance load
100
k
CL
Capacitance load
15
pF
VBAT UNDERVOLTAGE ELECTRICAL CHARACTERISTICS(5)
2.7 < VBAT < 3.1, Full scale code digital input
2.45
VO(AFC)
Output voltage
2.7 < VBAT < 3.1, Zero scale code digital input
0.25
V
2.7 < VBAT < 3.1, Input code = 80h
1.35
(1)
Not production tested. Assured by using the reference EVM.
(2)
REG_EN pin = Low, includes reference block and PAVREF.
(3)
Includes power consumption of the reference block.
(4)
r[PSCNTAFC] is the name of a register command by serial interface.
(5)
AFC DAC is the only functional operation. The electrical characteristics are typical, but not specified.
18
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