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參數(shù)資料
| 型號： | TPS65040ZQER |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 電源管理 |
| 英文描述： | 8-CHANNEL POWER SUPPLY MANAGEMENT CKT, PBGA71 |
| 封裝： | 5 X 5 MM, 0.50 MM PITCH, GREEN, PLASTIC, MICRO, BGA-71 |
| 文件頁數(shù)： | 57/73頁 |
| 文件大小： | 1928K |
| 代理商： | TPS65040ZQER |
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VREF1, VREF2
SLVS708B – NOVEMBER 2006 – REVISED APRIL 2007
Table 15. SIN_SYSCLK1 Output Control
REG_EN(1)
SYSCLK_EN
SIN_SYSCLK1
1
ON
1
0
OFF
0
Don't Care
OFF
(1)
REG_EN sequence is described in SEQUENCE CONTROL.
Table 16. SIN_SYSCLK2 Output Control
REG_EN(1)
SYSCLK_EN
r[PSCNTSYSCLK_GSM]
SYSCLK_EN2
SIN_SYSCLK2
1
ON
1
0
1
OFF
1
0
1
0
OFF
1
0
1
OFF
1
0
OFF(2)
1
0
1
OFF(2)
1
0
OFF(2)
1
0
OFF
0
Don't Care
OFF
(1)
REG_EN sequence is described in SEQUENCE CONTROL.
(2)
The output voltage level of OFF state has VTCXO (2.85 V (typ)) level. Otherwise, it is 0 V level.
Table 17. SIN_SYSCLK3 Output Control
REG_EN(1)
SYSCLK_EN
r[PSCNTSYSCLK_UMTS]
WRFON
SIN_SYSCLK3
1
ON
1
0
1
OFF
1
0
1
0
OFF
1
0
1
OFF
1
0
OFF(2)
1
0
1
OFF(2)
1
0
OFF(2)
1
0
OFF
0
Don't Care
OFF
(1)
REG_EN sequence is described in SEQUENCE CONTROL.
(2)
The output voltage level of OFF state has VTCXO [2.85 V (typ)] level. Otherwise is 0 V level.
The TPS65040 adopts the bandgap circuit and the highly accurate bias current source as an internal standard
voltage. There are two kinds of bandgap circuits, Sub bandgap and Main bandgap. The Sub bandgap circuit, of
the low-power consumption mode, always powers up when REG_EN=High. The Main bandgap circuit powers up
when the normal mode of the LDO, and other blocks are powered up. The highly accurate bias current source
also powers up when Main bandgap powers up; and, the bias current is supplied to each block. Bandgap output
is distributed using two buffer amplifiers, and are output to the VREF1 pin and the VREF2 pin respectively.
VREF2 pin outputs the Sub-bandgap while Sub bandgap is powered up, and Main bandgap is powered down.
When Main bandgap powers up, Main bandgap is output from the VREF2 pin. VREF1 pin only outputs Main
bandgap. When Main bandgap is powered down or r[PSCNTDC/DC] is set to low, VREF1 pin goes to 0V. The
block diagram circuit is shown in Figure 82.
60
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