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參數(shù)資料
| 型號： | TPS65040ZQER |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 電源管理 |
| 英文描述： | 8-CHANNEL POWER SUPPLY MANAGEMENT CKT, PBGA71 |
| 封裝： | 5 X 5 MM, 0.50 MM PITCH, GREEN, PLASTIC, MICRO, BGA-71 |
| 文件頁數(shù)： | 45/73頁 |
| 文件大小： | 1928K |
| 代理商： | TPS65040ZQER |
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ABSOLUTE MAXIMUM RATINGS
DISSIPATION RATINGS
(1)
SLVS708B – NOVEMBER 2006 – REVISED APRIL 2007
ORDERING INFORMATION
PART NUMBER
TA
PACKAGE(1)
ORDERING
PACKAGE MARKING
TPS65040
–30
°C to 85°C
71-pin MicroStar Junior
TPS65040ZQE
PS65040
(1)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
over operating free-air temperature range (unless otherwise noted) (1)
VALUE
UNIT
VIO1V8 pin with respect to GND2
–0.3 to 3.3
V
VBN1 pin with respect to GND1
–0.3 to 5.5
V
VBN2 pin with respect to GND2
–0.3 to 5.5
V
VBN3 pin with respect to GND3
–0.3 to 5.5
V
Supply voltage
VBN4 pin with respect to GND4
–0.3 to 5.5
V
VBN5 pin with respect to GND5
–0.3 to 5.5
V
VBDDP(2) pin with respect to DDGNDP(2)
–0.3 to 5.5
V
DDINA pin with respect to DDGNDA
–0.3 to 5.5
V
Input voltage range on REG_EN pin with respect to GND2
–0.3 to 5.5
V
Input voltage range on PABIAS1, PA_FB and ERR pins with respect to DDGNDA
–0.3 to 5.5
V
Input voltage range(2) on L1 and L2 pins with respect to DDGNDP
–0.3 to 5.5
V
Input voltage range on other pins(3)
–0.3 to 5.5
V
Input voltage range on SYSCLK_IN pin with respect to GND6
–0.3 to 3.3
V
Input voltage range on other input pins(4)
–0.3 to 3.3
V
Input voltage range on other pins(5)
–0.3 to 3.3
V
Peak LDO and SW output current(6)
Internally Limited
Peak current of power path(2) on VBDDP, L1, L2 pins with respect to DDGNDP
5
A
Storage temperature
–40 to 150
°C
Maximum junction temperature
125
°C
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability
(2)
VBDDP is A4 and B4 pins, L1 is A5 and B5 pins, L2 is A7 and B7 pins, and DDGNDP is A6 and B6 pins.
(3)
Pin is VTCXO with respect to GND3. Pins are VGGE1_V28, VGGE2_V28, and VGGE3_V28 with respect to GND5. Pin is VOUT with
respect to DDGNDP. Pin is TEST with respect to DDGNDA.
(4)
Pins are CCLK, CDATA, CSTB, TSPCLK, TSPDIN, TSPEN, CRESET, WRFON, TXON, TXONFST, TBNDSEL1, TBNDSEL2,
SYSCLK_EN and SYSCLK_EN2 with respect to GND2.
(5)
Pins are AFC, PAVREF1, PAVREF2, and PAVREF3 with respect to GND1. Pins are SIN_SYSCLK1, SIN_SYSCLK2 and
SIN_SYSCLK3 with respect to GND6.
(6)
LDO and SW OUTPUT are V11_V28TX, PA_VDD, V12_V28RX, V_LNA_FEM, V15_V18A , V13_V28A, VTCXO, VGGE1_V28,
VGGE2_V28 and VGGE3_V28.
MAX POWER DISSIPATION
DERATING FACTOR
PACKAGE
RθJA
AT TA = 25°C
TA < 25°C
ZQE
51.23
°C/W
1.95 W
19.52 mW/
°C
(1)
Test board conditions
JEDEC High-K (2S2P) board used
3x3 inch, 4 layer
1 oz copper ground/power trace in the PCB
2 oz copper trace on the top/bottom of the PCB
5
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