參數(shù)資料
型號(hào)： TPS65040ZQER
廠商： TEXAS INSTRUMENTS INC
元件分類： 電源管理
英文描述： 8-CHANNEL POWER SUPPLY MANAGEMENT CKT, PBGA71
封裝： 5 X 5 MM, 0.50 MM PITCH, GREEN, PLASTIC, MICRO, BGA-71
文件頁(yè)數(shù)： 38/73頁(yè)
文件大?。?/td> 1928K
代理商： TPS65040ZQER
BUCK-BOOST DC/DC CONVERTER POWER-UP SEQUENCE AND MODE STATE DESCRIPTION
Power-Up Sequence
PABIAS1 Pin Input Voltage Range
Disable Mode
Active Discharge When Disable Mode
Idle Mode
Softstart Mode
Normal Operation Mode
SLVS708B – NOVEMBER 2006 – REVISED APRIL 2007
Table 2. Low/High Control for External DC/DC Converter (continued)
REG_EN(1)
VIO1V8(1)
TXONFST
r[PSCNTDC/DC_EXT]
EXT_DC_DC_ON_OFF
1
0
Low
1
0
Low
0
Don't Care
Low
1
0
Don't Care
Low
Pin PABIAS1 controls the output voltage and must have an input to set the output voltage before power up of
the DC/DC converter. If PABIAS1 pin has an unknown voltage, the DC/DC converter can not regulate the output
voltage; and, the device or peripheral components may be damaged. Figure 72 shows the power-up sequence
for the DC/DC converter: (a) via an external pin controlled by TXONFST, and (b) via a register command control.
Figure 72 shows each mode from OFF (Disable Mode) to ON (Normal Operation Mode). The following
paragraphs give more details.
The input voltage range of PABIAS1 pin is from 0.4 V to 2.414 V. This range keeps the output voltage of the
DC/DC converter at the proper level. Also, it must be input before power-up of the DC/DC converter.
Table 1 shows the buck-boost DC/DC converter is disabled when TXONFST = Low, or r[PSCNTDC/DC] = Low.
Then the analog circuit of Figure 70 is disabled and the logic circuit is reset. Also, current-limit protection and
short-circuit protection are disabled.
VOUT output is pulled down to 0V when the buck-boost DC/DC converter is disabled. Then MN1, MP2 = ON
and MP1, MN2 = OFF in Figure 70. VOUT pin is pulled down to 0V via the coil, but when VOUT is below 0.6 V,
the discharging speed is at a gentle slope. Because the power supply of the MN2 and its gate driver buffer in
Figure 70 are supplied from VOUT, the MN2 cannot discharge the VOUT to 0V.
Table 1 shows the DC/DC converter is enabled when TXONFST = High and r[PSCNTDC/DC] = High. Figure 72
shows each mode during power-up sequence. Since the analog circuit is unstable, output transistors (MP1,
MN1, MP2, MN2) operate after 50
s (typ), counted by an internal oscillator. After the count-up it shifts to
softstart mode. Current-limit protection and short-circuit protection are disabled. Figure 72 shows the same
sequence; that is, TXONFST turns from low to high at r[PSCNTDC/DC] = High, and r[PSCNTDC/DC] turns low
to high at TXONFST = High.
Softstart mode operates to avoid rush current when the buck-boost DC/DC converter activates the output
transistor via idle mode. Internal VREF_SS ramps up within 500
s (max) by counter, when idle mode shifts to
softstart mode. Output voltage is set by PABIAS1 pin. The time of softstart mode depends on the value of the
output voltage. SS_OK = High finishes softstart mode when VREF_SS is counted up. After completing softstart
mode, current-limit protection and short-circuit protection start operation simultaneously.
Normal operation mode provides line regulation, load regulation, and fast transient response control by the
analog input of PABIAS1 pin. Current-limit and short-circuit protection are enabled continuously.
43
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