V15_V18A
VGGE1_V28
SLVS708B – NOVEMBER 2006 – REVISED APRIL 2007
Table 7. V13_V28A ON/OFF and Normal Mode/Low Power Mode Control
REG_EN(1)
VIO1V8(1)
CRESET(1)
WRFON
r[PSCNT13]
V13_V28A
1
Normal Mode
1
0
1
Low Power Mode
1
0
OFF
1
0
OFF
0
Don't Care
OFF
1
0
Don't Care
OFF
1
0
Don't Care
1
Normal Mode
(1)
REG_EN, VIO1V8 and CRESET sequence is described in SEQUENCE CONTROL.
V15_V18A is an LDO that outputs 1.85 V, and is powered up during the power-up sequence of the TPS65040.
The SEQUENCE CONTROL Section provides more detail. Normal mode and low-power mode can be selected.
Normal mode provides high performance, and low-power mode provides low current consumption. The output
PMOS is stopped when the load current exceeds the limit value of the current-limit protection circuit in normal
mode; the power supply is shut down. When the load current falls below the limit values, current limit is
released. Current-limit protection is not available in the low-power mode. This LDO has a low-current mode and
a high-current mode in normal mode. The low-current mode and high-current mode correspond to light-load and
heavy-load conditions, respectively. The modes are changed automatically. This LDO on/off is controlled by
r[PSCNT15], and switches from normal mode to low-power mode with the WRFON pin. Register command
r[PSCNT15] can be controlled through the serial interface; default is 1. The SERIAL INTERFACE Section
provides greater detail. Note that the electrical characteristics of this LDO are not assured for the range of 2.7V
< VBAT < 3.1V function. When not used, turn it off or to the low-power mode. On/off control of V15_V18A and
switch control for normal mode/low-power mode are shown in
Table 8.Table 8. V15_V18A ON/OFF and Normal Mode/Low Power Mode Control
REG_EN(1)
VIO1V8(1)
CRESET(1)
WRFON
r[PSCNT15]
V15_V18A
1
Normal Mode
1
0
1
Low Power Mode
1
0
OFF
1
0
OFF
0
Don't Care
OFF
1
0
Don't Care
OFF
1
0
Don't Care
1
Normal Mode
(1)
REG_EN, VIO1V8 and CRESET sequence is described in SEQUENCE CONTROL.
VGGE1_V28 is an LDO that outputs 2.85 V, and is one of the LDOs enabled during the power-up sequence of
the TPS65040. More detail is given in the SEQUENCE CONTROL Section. The normal mode and low-power
mode can be selected, where normal mode provides high performance, and low-power mode provides low
current consumption. The output PMOS is stopped when the load current exceeds the limit value for the
current-limit protection circuit in normal mode, and the power supply is shut down. When the load current falls
below the limit value, current limit is released. Current-limit protection is not available in the low-power mode.
This LDO has a low-current mode and a high-current mode in normal mode. The low-current mode and
high-current mode correspond to light-load and heavy-load conditions, respectively. The modes are changed
automatically. LDO on/off is controlled by register command r[PSCNTGGE1]. Normal mode and low-power
mode are switched using register command r[GGE1psmode] at r[GGEmodecnt]=High, SYSCLK_EN2 pin at
r[GGEmodecnt]=Low. Register commands r[PSCNTGGE1], r[GGEmodecnt], and r[GGE1psmode] can be
controlled through the serial interface; the default is 1. More detail is provided in the SERIAL INTERFACE
Section. Note that the electrical characteristics for this LDO are not assured within the range of
3.0V<VBAT<3.1V function. Moreover, the output voltage also decreases by VBAT–VSAT, when VBAT
decreases. Turn off this LDO, or use the low-power mode, when in the VBAT<3 V condition. On/off control of
VGGE1_V28 and the switch control of normal mode/low-power mode are shown in
Table 9.53