參數(shù)資料
型號: TPS65072TRSLRQ1
廠商: TEXAS INSTRUMENTS INC
元件分類: 電源管理
英文描述: POWER SUPPLY SUPPORT CKT, PQCC48
封裝: 6 X 6 MM, 0.4 MM PITCH, PLASTIC, QFN-48
文件頁數(shù): 7/90頁
文件大小: 1375K
代理商: TPS65072TRSLRQ1
www.ti.com
SLVSAP7 – JANUARY 2011
PIN FUNCTIONS (continued)
PIN
I/O
DESCRIPTION
NAME
NO.
Power_ON input for the internal state machine. After PB_IN was pulled LOW to turn on the TPS6507x, the
POWER_ON pin needs to be pulled HIGH by the application processor to keep the system in ON-state
POWER_ON
13
I
when PB_IN is released HIGH. If POWER_ON is released LOW, the DCDC converters and LDOs will turn
off when PB_IN is HIGH.
Open drain output. This pin is driven by the status of the /PB_IN input (after debounce). PB_OUT=LOW if
PB_OUT
24
O
PB_IN=LOW
Open drain power good output. The delay time equals the setting for Reset. The pin will go low depending
PGOOD
26
O
on the setting in register PGOODMASK. Optionally it is also driven LOW for 0.5ms when PB_IN is pulled
LOW for >15s.
TPS65070, TPS65073, TPS650731, TPS650732:Input for the reset comparator. RESET will be LOW if this
THRESHOLD
47
I
voltage drops below 1V.
Open drain active low reset output, reset delay time. The status depends on the voltage applied at
RESET
39
O
THRESHOLD.
PowerPAD
Power ground connection for the PMU. Connect to GND
Copyright 2011, Texas Instruments Incorporated
15
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