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| 型號： | TPS65072TRSLRQ1 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 電源管理 |
| 英文描述： | POWER SUPPLY SUPPORT CKT, PQCC48 |
| 封裝： | 6 X 6 MM, 0.4 MM PITCH, PLASTIC, QFN-48 |
| 文件頁數(shù)： | 89/90頁 |
| 文件大?。?/td> | 1375K |
| 代理商： | TPS65072TRSLRQ1 |
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www.ti.com
SLVSAP7 – JANUARY 2011
wLED BOOST CONVERTER
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VL4
voltage at L4 pin
2.8
39
V
Vsink1,2
Input voltage at ISINK1, ISINK2 pins
16
V
VOUT
Internal overvoltage protection
35
37
39
V
Maximum boost factor (Vout/Vin)
Isink1 = Isink2 = 20 mA, Vin = 2.8 V
9
10
Tmin_off
Minimum off pulse width
70
ns
RDS(ON)
N-channel MOSFET on-resistance
VL4 = 3.6 V
0.6
N-channel MOSFET current limit
0.8
1.6
2.0
A
ILN_NFET
N-channel leakage current
VDS = 25 V, TA = 25°C
1
mA
Switching frequency
1.125
MHz
Vsink1,
Minimum voltage drop at Isink pin to GND for
400
mV
Vsink2
proper regulation
VISET
ISET pin voltage
1.24
V
Iset current = 15 mA
1000
KISET
Current multiple Iout/Iset
Iset current = 25 mA
1000
Minimum current into ISINK1, ISINK2 pins
For proper dimming (string can be disabled also)
4
mA
Isink1, Isink2
Maximum current into ISINK1, ISINK2 pins
Vin = 3.3 V
25
mA
DC current set accuracy
Isinkx = 5 mA to 25 mA; no PWM dimming
±5%
Rset1 = 50k; Isink1 = 25 mA, Vin = 3.6 V; no PWM
Current difference between Isink1 and isink2
±5%
dimming
Rset2 = 250k; Isink1 = 5 mA, Vin = 3.6 V; no PWM
Current difference between Isink1 and Isink2
±5%
dimming
PWM dimming Bit = 00
–15%
100
15%
PWM dimming Bit = 01 (default)
–15%
200
15%
fPWM
PWM dimming frequency
PWM dimming Bit = 10
–15%
500
15%
Hz
PWM dimming Bit = 11
–15%
1000
15%
Rise / fall time of PWM signal
For all PWM frequencies
2
ms
Dimming PWM DAC resolution
1%
Reset, PB_IN, PB_OUT, PGood, Power_on, INT, EN_EXTLDO, EN_wLED
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
–15%
20
15%
Input voltage at threshold pin rising; time
100(1)
Reset delay time and PGOOD delay time
defined with <PGOOD DELAY0>, <PGOOD
ms
200
DELAY1>
400
PB-IN debounce time
–15%
50
15%
ms
PB_IN “Reset-detect- time”
Internal timer
–15%
15
15%
s
PGOOD low time when PB_IN = Low for >15s
–15%
0.5
15%
ms
VIH
High level input voltage on pin POWER_ON
1.2
VIN
V
VIH
High level input voltage on pin PB_IN
1.8
AVDD6
V
VIL
Low Level Input Voltage, PB_IN, Power_on
0
0.4
V
Internal pull-up resistor from PB_IN to AVDD6
50
k
Output current at AVDD6
1
mA
IIN
Input bias current at Power_on
0.01
1.0
mA
Reset, PB_OUT, PGood, INT output low voltage,
VOL
IOL = 1 mA, Vthreshold < 1 V
0.3
V
EN_EXTLDO
VOH
EN_EXTLDO HIGH level output voltage
IOH = 0.1 mA; optional push pull output
VSYS
V
IOL
Reset, PB_OUT, PGood, INT sink current
1
mA
Reset, PB_OUT, PGood, INT open drain
Reset, PB_OUT, PGood,INT output leakage current
0.25
mA
output in high impedance state
Vth
Threshold voltage at THRESHOLD pin
Input voltage falling
–4%
1
4%
V
Vth_hyst
Hysteresis on THRESHOLD pin
Input voltage rising
7
mV
Iin
Input bias current at EN_wLED, THRESHOLD
1
mA
(1)
Default Reset delay time is set to 100 ms typical
Copyright 2011, Texas Instruments Incorporated
9
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