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參數(shù)資料
| 型號： | TS(X)PC603EMAU3LL |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 100 MHz, RISC PROCESSOR, CQFP240 |
| 封裝： | CERAMIC, QFP-240 |
| 文件頁數(shù)： | 2/38頁 |
| 文件大?。?/td> | 632K |
| 代理商： | TS(X)PC603EMAU3LL |
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TSPC603E
10/38
Signal name
Signal
type
Signal function
Mnemonic
L2_TSTCLK
LSSD test control signal for factory use only
Input
Machine Check Inter-
rupt
MCP
Initiates a machine check interrupt operation if the bit ME of MSR regis-
ter and bit EMCP of HID0 register are set
Input
PLL Configuration
PLL_CFG[0-3]
Configures the operation of the PLL and the internal processor clock
frequency
Input
Quiescent
Acknowledge
QACK
All bus activity has terminated and the 603e may enter a quiescent (or
low power) state
Input
Quiescent Request
QREQ
Is requesting all bus activity normally to enter a quiescent (low power)
state
Output
Reservation
RSRV
Represents the state of the reservation coherency bit in the reservation
address register
Output
System Management
Interrupt
SMI
Initiates a system management interrupt operation if the bit EE of MSR
register is set
Input
Soft Reset
SRESET
Initiates processing for a reset exception
Input
System Clock
SYSCLK
Represents the primary clock input for the 603e, and the bus clock fre-
quency for 603e bus operation
Input
Transfer Acknowledge
TA
A single-beat data transfer completed successfully or a data beat in a
burst transfer completed successfully
Input
Timebase Enable
TBEN
The timebase should continue clocking
Input
Transfer Burst
TBST
If output, a burst transfer is in progress
If input, when snooping for single-beat reads
I/O
Transfer Code
TC[0-1]
Special encoding for the transfer in progress
Output
Test clock
TCK
Clock signal for the IEEE P1149.1 test access port (TAP)
Input
Test data input
TDI
Serial data input for the TAP
Input
Test data output
TDO
Serial data output for the TAP
Output
Transfer Error
Acknowledge
TEA
A bus error occurred
Input
TLBI Sync
TLBISYNC
Instruction execution should stop after execution of a tlbsync instruction
Input
Test mode select
TMS
Selects the principal operations of the test-support circuitry
Input
Test reset
TRST
Provides an asynchronous reset of the TAP controller
Input
Transfer Size
TSIZ[0-2]
For memory accesses, these signals along with TBST indicate the data
transfer size for the current bus operation
I/O
Transfer start
TS
If output, begun a memory bus transaction and the address bus and
transfer attribute signals are valid
If input, another master has begun a bus transaction and the address
bus and transfer attribute signals are valid for snooping (see GBL)
I/O
Transfer Type
TT[0-4]
Type of transfer in progress
I/O
Write-Through
WT
A single-beat transaction is write-through
Output
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