參數(shù)資料
型號(hào)： TS(X)PC603EMAU3LL
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 100 MHz, RISC PROCESSOR, CQFP240
封裝： CERAMIC, QFP-240
文件頁(yè)數(shù)： 24/38頁(yè)
文件大小： 632K
代理商： TS(X)PC603EMAU3LL
TSPC603E
30/38
The PowerPC architecture support four types of exceptions :
D Synchronous, precise - These are causes by instructions. All instruction-caused exceptions are handled precisely ; that is, the
machine state at the time the exception occurs is known and can be completely restored. This means that (excluding the trap and
system call exceptions) the address of the faulting instruction is provided to the exception handler and that neither the faulting
instruction nor subsequent instructions in the code stream will complete execution before the exception is taken. Once the excep-
tion is processed, execution resumes at the address of the faulting instruction (or at an alternate address provided by the exception
handler). When an exception is taken due to an trap or system call instruction, execution resumes at an address provided by the
handler.
D Synchronous, imprecise - The PowerPC architecture defines two imprecise floating-point exception modes, recoverable and
nonrecoverable. Even though the 603e provides a means to enable he imprecise modes, it implements these modes identically
to the precise mode (-hat is, all enabled floating-point enabled exceptions are always precise on the 603e).
D Asynchronous, maskable - The external, SMI, and decrementer interrupts are maskable asynchronous exceptions. When
these exceptions occur, their handling is postponed until the next instruction, and any exceptions associated with that instruction,
completes execution. If there are no instructions in the execution units, the exception is taken immediately upon determination
of the correct restart address (for loading SRR0).
D Asynchronous, non maskable - There are two non maskable asynchronous exceptions : system reset and the machine check
exception. These exceptions may not be recoverable, or may provide a limited degree of recoverability. All exceptions report
recoverability through the SMR[RI] bit.
5.4.2. PowerPC 603e microprocessor exception model
A specified by the PowerPC architecture, all 603e exceptions can be described as either precise or imprecise and either synchronous
or asynchronous. Asynchronous exceptions (some or which are maskable) are caused by events external to the processor’s execu-
tion ; synchronous exceptions, which are all handled precisely by the 603e, are caused by instructions. The 603e exception classes
are shown in Table 14.
Synchronous/Asynchronous
precise/Imprecise
Exception type
Asynchronous, non maskable
Imprecise
Machine check
System reset
Asynchronous, maskable
Precise
External interrupt
Decrementer
System management interrupt
Synchronous
Precise
Instruction-caused exceptions
Table 15 : PowerPC 603e microprocessor exception classifications
Although exceptions have other characteristics as well, such as whether they are maskable or non maskable, the distinctions shown
in Table 15 define categories of exceptions that the 603e handles uniquely. Note that Table 15 includes no synchronous imprecise
instructions. While the PowerPC architecture supports imprecise handling of floating-point exceptions, the 603e implements these
exception modes as precise exceptions.
The 603e’s exceptions, and conditions that cause them, are listed in Table 16. Exceptions that are specific to the 603e are indicated.
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