參數(shù)資料
型號(hào)： TS(X)PC603EMAU3LL
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 100 MHz, RISC PROCESSOR, CQFP240
封裝： CERAMIC, QFP-240
文件頁(yè)數(shù)： 31/38頁(yè)
文件大?。?/td> 632K
代理商： TS(X)PC603EMAU3LL
TSPC603E
37/38
9. CLOCK RELATIONSHIPS CHOICE
The 603e microprocessors offer customers numerous clocking options. An internal phase-lock loop synchronizes the processor
(CPU) clock to the bus or system clock (SYSCLK) at various ratios.
Inside each PowerPC microprocessor is a phase-lock loop circuit. A voltage controlled oscillator (VCO) is precisely controlled in
frequency and phase by a frequency/phase detector which compares the input bus frequency (SYSCLK frequency) to a submultiple
of the VCO.
The ratio of CPU to SYSCLK frequencies is often referred to as the bus mode (for example, 2:1 bus mode).
In the Table (Table 17), the horizontal scale represents the bus frequency (SYSCLK) and the vertical scale represents the PLL–
CFG[0–3] signals.
For a given SYSCLK (bus) frequency, the PLL configuration signals set the internal CPU and VCO frequency of operation.
Table 17 : CPU frequencies for common bus frequencies and multipliers
CPU Frequency in MHZ (VCO Frequency in MHz)
PLL_CFG[0–3]
Bus–to–
Core
Multiplier
Core–to
VCO
Multiplier
Bus
20 MHz
Bus
25 MHz
Bus
33.33
MHz
Bus
40 MHz
Bus
50 MHz
Bus
60 MHz
Bus
66.67
MHz
0000
1x
2x
–
0001
1x
4x
–
0010
1x
8x
–
1100
1.5x
2x
–
90
(180)
100
(200)
0100
2x
–
80
(160)
100
(200)
120
(240)
133.33
(266)
0101
2x
4x
–
0110
2.5x
2x
–
83.33
(166)
100
(200)
125
(250)
–
1000
3x
2x
–
100
(200)
120
(240)
–
1110
3.5x
2x
–
87.5
(175)
116.67
(233)
–
1010
4x
2x
80
(160)
100
(200)
133.33
(266)
–
0011
PLL bypass
1111
Clock off
Notes :
1. Some PLL configurations may select bus, CPU or VCO frequencies which are not supported
2. In PLL–bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is disabled, and
the bus mode is set for 1:1 mode operation. This mode is intended for factory use only.
Note : the AC timing specifications given in this document do not apply in PLL–bypass mode.
3. In clock–off mode, no clocking occurs inside the 603e regardless of the SYSCLK input.
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