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參數(shù)資料
| 型號： | TS68230P |
| 廠商： | 意法半導體 |
| 英文描述： | HMOS PARALLEL INTERFACE/TIMER |
| 中文描述： | HMO的并行接口/定時器 |
| 文件頁數(shù)： | 22/61頁 |
| 文件大?。?/td> | 2911K |
| 代理商： | TS68230P |
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PACR
7 6
0 1
Port A Submode
Submode 01
PACR
5 4 3
0 X X
1 0 0
1 0 1
1 1 0
1 1 1
H2 Control
Input pin - edge-sensitive status inputs, H2S is set on an asserted edge.
Output pin - negated, H2S is always clear.
Output pin - asserted, H2S is always clear.
Output pin - interlocked input handshake protocol, H2S is always clear.
Output pin - pulsed input handshake protocol, H2S is always clear.
PACR
2
0
1
H2 Interrupt Enable
The H2 interrupt is disabled.
The H2 interrupt is enabled.
PACR
1
0
1
H1 SVCRQ Enable
The H1 interrupt and DMA request are disabled.
The H1 interrupt and DMA request are enabled.
PACR
0
0
It is clear when both latches are full and cannot accept new data.
1
The H1S status bit is one when both of the port A output latches are empty. It is clear when at
least one latch is full.
H1 Status Control
The H1S status bit is set when either the port A initial or final output latch can accept new data
PBCR
7 6
0 1
Port B Submode
Submode 01
PBCR
5 4 3
0 X X
1 0 0
1 0 1
1 1 0
1 1 1
H4 Control
Input pin - edge-sensitive status input, H4S is set on an asserted edge.
Output pin - negated, H4S is always cleared.
Output pin - asserted, H4S is always cleared.
Output pin - interlocked input handshake protocol, H4S is always cleared.
Output pin - pulsed input handshake protocol, H4S is always cleared.
Programmable Options Mode 0 - Port A Submode 01 and Port B Submode 01
TS68230
22/61
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相關代理商/技術參數(shù) |
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| TS68302CR1B/C16 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Integrated Multiprotocol Processor IMP |
| TS68302CR1B/T16 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Integrated Multiprotocol Processor IMP |
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