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參數(shù)資料
| 型號： | TS68230P |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | HMOS PARALLEL INTERFACE/TIMER |
| 中文描述： | HMO的并行接口/定時器 |
| 文件頁數(shù)： | 36/61頁 |
| 文件大?。?/td> | 2911K |
| 代理商： | TS68230P |
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PROGRAMMER’S MODEL
This section describes the internal accessible regis-
ter organization as represented in table 1.3 located
at the end of this document and in table 4.1. Address
space within the address map is reserved for future
expansion.
Table 4.1 :
PI/T Register Addressing Assignments
.
Register
Select Bits
5 4 3 2 1
0 0 0 0 0
0 0 0 0 1
0 0 0 1 0
0 0 0 1 1
0 0 1 0 0
0 0 1 0 1
0 0 1 1 0
0 0 1 1 1
0 1 0 0 0
0 1 0 0 1
0 1 0 1 0
0 1 0 1 1
0 1 1 0 0
0 1 1 0 1
1 0 0 0 0
1 0 0 0 1
1 0 0 1 1
1 0 1 0 0
1 0 1 0 1
1 0 1 1 1
1 1 0 0 0
1 1 0 0 1
1 1 0 1 0
Register
Accessible
Affected by
Reset
Affected by
Read Cycle
Port General Control Register
Port Service Request Register
Port A Data Direction Register
Port B Data Direction Register
Port C Data Direction Register
Port Interrupt Vector Register
Port A Control Register
Port B Control Register
Port A Data Register
Port B Data Register
Port A Alternate Register
Port B Alternate Register
Port C Data Register
Port Status Register
Timer Control Register
Timer Interrupt Vector Register
Counter Preload Register High
Counter Preload Register Middle
Counter Preload Register Low
Count Register High
Count Register Middle
Count Register Low
Timer Status Register
(PGCR)
(PSRR)
(PADDR)
(PBDDR)
(PCDDR)
(PIVR)
(PACR)
(PBCR)
(PADR)
(PBDR)
(PAAR)
(PBAR)
(PCDR)
(PSR)
(TCR)
(TIVR)
(CPRH)
(CPRM)
(CPRL)
(CNTRH)
(CNTRM)
(CNTRL)
(TSR)
R W
R W
R W
R W
R W
R W
R W
R W
R W
R W
R
R
R W
R W*
R W
R W
R W
R W
R W
R
R
R
R W*
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
Yes
Yes
Yes
No
No
No
No
No
No
Yes
No
No
No
No
No
No
No
No
**
**
No
No
No
No
No
No
No
No
No
No
No
No
No
R = Read.
W = Write.
Throughout this section the following conventions
are maintained :
1. A read from a reserved location in the map re-
sults in a read from the "null register". The null
register returns all zeros for data and results in
a normal bus cycle. A write to one of these lo-
cations results in a normal bus cycle, but writ-
ten data is ignored.
2. Unused bits of a defined register are denoted
by "*" and are read as zeros ; written data is i-
gnored.
3. Bits that are unused in the chosen mode/sub-
mode but are used in others are denoted by
"X", and are readable and writable. Their
content, however, is ignored in the chosen
mode/submode.
4. All registers are addressable as 8-bit quanti-
ties. To facilitate operation with the MOVEP
instruction and the DMAC, addresses are or-
dered such that certain sets of registers may
also be accessed as words (two bytes) or long
words (four bytes).
SECTION 4
*
A write to this register may perform a special resetting opera-
TS68230
36/61
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