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參數(shù)資料
| 型號： | TS68230P |
| 廠商： | 意法半導體 |
| 英文描述： | HMOS PARALLEL INTERFACE/TIMER |
| 中文描述： | HMO的并行接口/定時器 |
| 文件頁數(shù)： | 23/61頁 |
| 文件大?。?/td> | 2911K |
| 代理商： | TS68230P |
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PBCR
2
0
1
H4 Interrupt Enable
The H4 interrupt is disabled.
The H4 interrupt is enabled.
PBCR
1
0
1
H3 SVCRQ Enable
The H3 interrupt and DMA request are disabled.
The H3 interrupt and DMA request are enabled.
PBCR
0
0
It is clear when both latches are full and cannot accept new data.
1
The H3S status bit is one when both of the port B output latches are empty. It is clear when at
least one latch is full.
H3 Status Control
The H3S status bit is set when either the port B initial or final output latch can accept new data.
3.3.3. SUBMODE 1X - BIT I/O (PIN-DEFINABLE
SINGLE-BUFFERED OUTPUT OR NON-LAT-
CHED INPUT). In mode 0, simple bit I/O is available
by programming submode 1X in the desired port’s
control register. This submode is intended for appli-
cations in which several independent devices must
be controlled or monitored. Data written to the as-
sociated (input/output) register is single buffered. If
the data direction register bit for that pin is a one
(output), the output buffer is enabled. If it is a zero
(input) data written is still latched, but is not available
at the pin. Data read from the data register is the in-
stantaneous value of the pin or what was written to
the data register, depending on the contents of the
data direction register. H1(H3) is an edge-sensitive
status input pin only and it controls no data related
function. The H1S(H3S) status bit is set following the
asserted edge of the input waveform. It is cleared by
either the RESET pin being asserted, writing a one
to the associated status bit in the port status register
(PSR), or when the H12 enable (H34 enable) bit of
the port general control register is clear. H2 may be
programmed as :
1. H2(H4) may be an edge-sensitive status input
that is independent of H1(H3) and the transfer
of port data. On the asserted edge of H2(H4),
the H2S(H4S) status bit is set. It is cleared by
either the RESET pin being asserted, writing a
one to the particular status bit in the port status
register (PSR), or when the H12 enable (H34
enable) bit of the port general control register
is clear.
2. H2(H4) may be a general-purpose output pin
that is always negated. In this case the
H2S(H4S) status bit is always clear.
3. H2(H4) may be a general-purpose output pin
that is always asserted. In this case the
H2S(H4S) status bit is always clear.
Programmable Options Mode 0 - Port A Submode 01 and Port B Submode 01
(continued)
TS68230
23/61
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相關代理商/技術參數(shù) |
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| TS68302 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Integrated Multiprotocol Processor IMP |
| TS68302CA1B/C16 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Integrated Multiprotocol Processor IMP |
| TS68302CA1B/T16 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Integrated Multiprotocol Processor IMP |
| TS68302CR1B/C16 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Integrated Multiprotocol Processor IMP |
| TS68302CR1B/T16 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Integrated Multiprotocol Processor IMP |
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