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參數(shù)資料
| 型號： | TS68230P |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | HMOS PARALLEL INTERFACE/TIMER |
| 中文描述： | HMO的并行接口/定時器 |
| 文件頁數(shù)： | 50/61頁 |
| 文件大?。?/td> | 2911K |
| 代理商： | TS68230P |
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6.6. AC ELECTRICAL SPECIFICATIONS
(V
CC
= 5.0Vdc
±
5%, V
SS
= 0Vdc, T
A
= T
L
to T
H
unless otherwise specified)
Read and Write Cycle Timings
(figures 6.2 and 6.3)
8MHz
Min.
0
100
30
10MHz
Min.
0
65
20
Number
Parameter
Max.
Max.
Unit
1
R/W, RS1-RS5 Valid to CS Low (setup time)
CS Low to R/W and RS1-RS5 Invalid (hold time)
CS Low to CLK Low (setup time)
CS Low to Data Out Valid
RS1-RS5 Valid to Data Out Valid
CLK Low to DTACK Low (read/write cycle)
DTACK Low to CS High (hold time)
CS or PIACK or TIACK High to Data Out Invalid (hold time)
CS or PIACK or TIACK High to D0-D7 High Impedance
CS or PIACK or TIACK High to DTACK High
CS or PIACK or TIACK High to DTACK High Impedance
Data In Valid to CS Low (setup time)
CS Low to Data in Invalid (hold time)
CLK low on which DMAREQ is asserted to CLK low on
which DMAREQ is negated
Read Data Valid to DTACK Low (setup time)
Synchronized CS to CLK low on which DMAREQ is asserted
CLK Low to DMAREQ Low (delay time)
CLK Low to DMAREQ High (delay time)
Synchronized H1(H3) to CLK low on which PIRQ is asserted
Synchronized CS to CLK low on which PIRQ is high impedance
CLK Low to PIRQ Low or High Impedance
TIN Frequency (external clock) - Prescaler used.
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2
(1)
3
(2)
4
(3)
5
6
7
(4)
8
9
10
11
12
13
23
75
140
70
60
100
60
0
0
0
0
0
0
50
50
100
45
45
55
0
0
100
2.5
65
2.5
3
3
CLK Per
28
32
(5)
35
36
37
(5)
38
(5)
39
40
(6)
0
3
0
0
3
3
0
0
0
3
0
0
3
3
0
0
ns
3
3
CLK Per
ns
ns
CLK Per
CLK Per
ns
f
clk
(Hz)
(7)
f
clk
(Hz)
(7)
ns
CLK Per
ns
ns
120
120
3
3
250
1
100
100
3
3
225
1
41
TIN Frequency (external clock) - Prescaler not used.
0
1/8
0
1/8
42
43
44
45
TIN Pulse Width High or Low (external clock)
TIN Pulse Width Low (run/halt control)
CLK Low to TOUT High, Low, or High Impedance
CS, PIACK, or TIACK High to CS, PIACK, or TIACK Low
by solving equations (1) and (2) iteratively for any value of T
A
.
55
1
0
50
45
1
0
30
250
225
Notes :
1. See
1.4. Bus Interface Operation
for exception.
2. This specification only applies if the PI/T had completed all operations initiated by the previous bus cycle when CS
was asserted. Following a normal read or write bus cycle, all operations are complete within three clocks after the
falling edge of the CLK pin on which DTACK was asserted. If CS is asserted prior to completion of these opera-
tions, the new bus cycle, and hence, DTACK is postponed.
If all operations of the previous bus cycle were complete when CS was asserted, this specification is made only to
insure that DTACK is asserted with respect to the falling edge of the CLK pin as shown in the timing diagram, not
to guarantee operation of the part. If the CS setup time is violated, DTACK may be asserted as shown, or may be
asserted one clock cycle later.
3. Assuming the RS1-RS5 to data valid time has also expired.
4. This specification imposes a lower bound on CS low time, guaranteeing that CS will be low for at least 1 CLK pe-
riod.
5. Synchronized means that the input signal has seen seen by the PI/T on the appropriate edge of the clock (rising
edge for H1(H3) and falling edge for CS). (Refer to the
1.4. Bus Interface Operation
for the exception concerning
CS).
6. This limit applies to the frequency of the signal at TIN compared to the frequency of the CLK signal during each
clock cycle. If any period of the waveform at TIN is smaller than the period of the CLK signal at that instant, then
it is likely that the timer circuit will completely ignore one cycle of the TIN signal.
If these two signals are derived from different sources they will have different instantaneous frequency variations. In
this case the frequency applied to the TIN pin must be distinctly less than the frequency at the CLK pin to avoid lost
cycles of the TIN signal. With signals derived from different crystal oscillators applied to the TIN and CLK pins with
TS68230
50/61
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