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參數(shù)資料
| 型號(hào)： | TS87C51RD2-VLMR |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 40 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | 1.40 MM HEIGHT, VQFP-64 |
| 文件頁數(shù)： | 52/83頁 |
| 文件大?。?/td> | 8336K |
| 代理商： | TS87C51RD2-VLMR |
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50
32117D–AVR-01/12
AT32UC3C
7.
Power Manager (PM)
Rev: 4.1.2.4
7.1
Features
Generates clocks and resets for digital logic
On-the-fly frequency change of CPU, HSB and PBx clocks
Sleep modes allow simple disabling of logic clocks and clock sources
Module-level clock gating through maskable peripheral clocks
Wake-up from internal or external interrupts
Automatic identification of reset sources
7.2
Overview
The Power Manager (PM) provides synchronous clocks used to clock the main digital logic in the
device, namely the CPU, and the modules and peripherals connected to the High Speed Bus
(HSB) and the Peripheral Buses (PBx).
The PM contains advanced power-saving features, allowing the user to optimize the power con-
sumption for an application. The synchronous clocks are divided into a number of clock
domains, one for the CPU and HSB, and one for each PBx. The clocks can run at different
speeds, allowing the user to save power by running peripherals relatively slow, whilst maintain-
ing high CPU performance. The clocks can be independently changed on-the-fly, without halting
any peripherals. The user may adjust CPU and memory speeds according to the dynamic appli-
cation load, without disturbing or re-configuring active peripherals.
Each module has a separate clock, enabling the user to save power by switching off clocks to
inactive modules. Clocks and oscillators can be automatically switched off during idle periods by
the CPU sleep instruction. The system will return to normal operation when interrupts occur.
The Power Manager also contains a Reset Controller, which collects all possible reset sources,
generates hard and soft resets, and allows the reset source to be identified by software.
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