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| 型號(hào)： | TSB41AB3 |
| 英文描述： | IC APEX 20KE FPGA 400K 672-FBGA |
| 中文描述： | 3個(gè)IEEE 1394a端口電纜收發(fā)器/仲裁器 |
| 文件頁數(shù)： | 31/50頁 |
| 文件大?。?/td> | 662K |
| 代理商： | TSB41AB3 |
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SLLS418G
–
JUNE 2000
–
REVISED JANUARY 2003
31
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
PHY-Link layer interface (continued)
There are four operations that may occur on the PHY-LLC interface: link service request, status transfer, data
transmit, and data receive. The LLC issues a service request to read or write a PHY register, to request the PHY
to gain control of the serial-bus in order to transmit a packet, or to control arbitration acceleration.
The PHY may initiate a status transfer either autonomously or in response to a register read request from the
LLC.
The PHY initiates a receive operation whenever a packet is received from the serial bus.
The PHY initiates a transmit operation after winning control of the serial-bus following a bus-request by the LLC.
The transmit operation is initiated when the PHY grants control of the interface to the LLC.
The encoding of the CTL0-CTL1 bus is shown in Table 10 and Table 11.
Table 10. CTL Encoding When PHY Has Control of the Bus
CTL0
CTL1
NAME
DESCRIPTION
0
0
Idle
No activity (this is the default mode)
0
1
Status
Status information is being sent from the PHY to the LLC.
1
0
Receive
An incoming packet is being sent from the PHY to the LLC.
1
1
Grant
The LLC has been given control of the bus to send an outgoing packet.
Table 11. CTL Encoding When LLC Has Control of the Bus
CTL0
CTL1
NAME
DESCRIPTION
0
0
Idle
The LLC releases the bus (transmission has been completed).
0
1
Hold
The LLC holds the bus while data is being prepared for transmission, or
another packet is to be transmitted (concatenated) without arbitrating.
1
0
Transmit
An outgoing packet is being sent from the LLC to the PHY.
1
1
Reserved
None
output differentiation
When an Annex J type isolation barrier is implemented between the PHY and LLC, the CTL0
–
CTL1, D0
–
D7,
and LREQ signals must be digitally differentiated so that the isolation circuits function correctly. Digital
differentiation is enabled on the TSB41AB3 when the ISO terminal is low.
The differentiation operates such that the output is driven either low or high for one clock period whenever the
signal changes logic state, but otherwise places the output in a high-impedance state for as long as the signal
logic state remains constant. On input, hysteresis buffers are used to convert the signal to the correct logic state
when the signal is high-impedance; the biasing network of the Annex J type isolation circuit pulls the signal
voltage level between the hysteresis thresholds of the input buffer so that the previous logic state is maintained.
The correspondence between the output logic state and the output signal level is shown in Figure 14.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TSB41BA3-EP | IC APEX 20KE FPGA 400K 672-FBGA |
| TSB41LV03PFP | IC APEX 20KE FPGA 600K 652-BGA |
| TSB41AB2I | IEEE 1394a-2000 TWO-PORT CABLE TRANSCEVER/ARBITER |
| TSB41LV03AI | IEEE 1394a THREE-PORT CABLE TRANSCEIVER/ARBITER |
| TSC692E | 672-pin FineLine BGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSB41AB3-EP | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394A-2000 THREE-PORT CABLE TRANSCEIVER/ARBITER |
| TSB41AB3IPFP | 功能描述:緩沖器和線路驅(qū)動(dòng)器 Three-Port Cable Xcvr/Arbiter RoHS:否 制造商:Micrel 輸入線路數(shù)量:1 輸出線路數(shù)量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
| TSB41AB3IPFP | 制造商:Texas Instruments 功能描述:IC TRX/ARBITER 1394A 3 PORT 80HTQFP |
| TSB41AB3IPFPEP | 功能描述:1394 接口集成電路 Mil Enh 3-Port Cable Xcvr/Arbiter RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB41AB3IPFPG4 | 制造商:Texas Instruments 功能描述:THREE PORT CBL TRNSCVR/ARBITER 1TX 1RX 400MBPS 80HTQFP - Rail/Tube |
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