參數(shù)資料
型號(hào)： TSB41AB3
英文描述： IC APEX 20KE FPGA 400K 672-FBGA
中文描述： 3個(gè)IEEE 1394a端口電纜收發(fā)器/仲裁器
文件頁(yè)數(shù)： 47/50頁(yè)
文件大?。?/td> 662K
代理商： TSB41AB3
SLLS418G
–
JUNE 2000
–
REVISED JANUARY 2003
47
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
interface reset and disable (continued)
The sequence of events for initialization of the PHY-LLC interface when the interface is in the differentiated
mode of operation (ISO terminal is low) is as follows:
1
a.
LPS reasserted. After the interface has been in the reset or disabled state for at least the minimum
T
RESTORE
time, the LLC causes the interface to be initialized and restored to normal operation by
reactivating the LPS signal. (In Figure 26, the interface is shown in the disabled state with SYSCLK
high-impedance inactive. However, the interface initialization sequence described here is also
executed if the interface is merely reset but not yet disabled.)
b.
SYSCLK activated. If the interface is disabled, the PHY reactivates its SYSCLK output when it detects
that LPS has been reasserted. If the PHY has entered a low-power state, it takes from 5.3 ms to 7.3 ms
for SYSCLK to be restored; if the PHY is not in a low-power state, SYSCLK is restored within 60 ns.
The PHY commences SYSCLK activity by driving the SYSCLK output low for half a cycle. Thereafter,
the SYSCLK output is a 50% duty cycle square wave with a frequency of 49.152 MHz
±
100 ppm (period
of 20.345 ns). Upon the first full cycle of SYSCLK, the PHY drives the CTL and D terminals low for one
cycle. The LLC is also required to drive its CTL, D, and LREQ outputs low during one of the first six
cycles of SYSCLK (in the above diagram, this is shown as occurring in the first SYSCLK cycle).
c.
Receive indicated. Upon the eighth SYSCLK cycle following reassertion of LPS, the PHY asserts the
receive state on the CTL lines and the data-on indication (all ones) on the D lines for one or more cycles
(because the interface is in the differentiated mode of operation, the CTL and D lines is in the
high-impedance state after the first cycle).
d.
Initialization complete. The PHY asserts the idle state on the CTL lines and logic 0 on the D lines. This
indicates that the PHY-LLC interface initialization is complete and normal operation may commence.
The PHY accepts requests from the LLC via the LREQ line.
SYSCLK
ISO
(High)
(a)
(c)
(b)
CTL0
D0
–
D7
LREQ
LPS
(d)
CTL1
7 Cycles
(d)
TCLK_ACTIVATE
Figure 27. Interface Initialization, ISO High
相關(guān)PDF資料
PDF描述
TSB41BA3-EP IC APEX 20KE FPGA 400K 672-FBGA
TSB41LV03PFP IC APEX 20KE FPGA 600K 652-BGA
TSB41AB2I IEEE 1394a-2000 TWO-PORT CABLE TRANSCEVER/ARBITER
TSB41LV03AI IEEE 1394a THREE-PORT CABLE TRANSCEIVER/ARBITER
TSC692E 672-pin FineLine BGA
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TSB41AB3-EP 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394A-2000 THREE-PORT CABLE TRANSCEIVER/ARBITER
TSB41AB3IPFP 功能描述:緩沖器和線路驅(qū)動(dòng)器 Three-Port Cable Xcvr/Arbiter RoHS:否 制造商:Micrel 輸入線路數(shù)量:1 輸出線路數(shù)量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel
TSB41AB3IPFP 制造商:Texas Instruments 功能描述:IC TRX/ARBITER 1394A 3 PORT 80HTQFP
TSB41AB3IPFPEP 功能描述:1394 接口集成電路 Mil Enh 3-Port Cable Xcvr/Arbiter RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
TSB41AB3IPFPG4 制造商:Texas Instruments 功能描述:THREE PORT CBL TRNSCVR/ARBITER 1TX 1RX 400MBPS 80HTQFP - Rail/Tube
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*